-
公开(公告)号：US20170153814A1
公开(公告)日：2017-06-01
申请号：US15360144
申请日：2016-11-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JUNGHWAN Ryu , Youngjin Cho , Hee Hyun Nam , Han-Ju Lee
CPC classification number: G06F3/061 , G06F3/0608 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F3/0685 , G06F12/0238 , G06F12/0246 , G06F2212/202 , G06F2212/401 , G11C11/005 , G11C11/1675 , G11C11/2275 , G11C13/0069 , G11C14/0036 , G11C14/0045 , G11C16/0483 , G11C16/10
Abstract: An access method of a storage device including heterogeneous nonvolatile memories includes receiving write-requested data; and writing the data in a first memory device or a second memory device based on a characteristic of the data, wherein the first memory device is capable of performing an overwrite operation and the second memory device is incapable of performing the overwrite operation.
-
公开(公告)号：US10331378B2
公开(公告)日：2019-06-25
申请号：US15188183
申请日：2016-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjin Cho , Hee Hyun Nam , Hyo-Deok Shin , Junghwan Ryu
Abstract: A method of operating a memory module can include receiving, at the memory module, an active command and an associated row address that indicates that the active command is directed to a volatile memory device included in the memory module or to a non-volatile memory device included in the memory module. The volatile memory device or the non-volatile memory device can be activated based on the associated row address in response to the active command. Status information can be provided at the memory module indicating readiness of the memory module for receipt of an operation command associated with the active command and the associated row address.
-
公开(公告)号：US20160357462A1
公开(公告)日：2016-12-08
申请号：US15096877
申请日：2016-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hee Hyun Nam , Jaegeun Park , Sungyong Seo , Youngkwang Yoo , Han-Ju Lee , Youngjin Cho
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0613 , G06F3/0616 , G06F3/0656 , G06F3/0659 , G06F3/068 , G06F3/0685
Abstract: Disclosed is a nonvolatile memory module. The nonvolatile memory module includes at least one nonvolatile memory, a random access memory (RAM) and a device controller. Responsive to receiving a write request comprising sub-data from a host, the device controller accumulates the sub-data in the RAM and programs the accumulated sub-data in the nonvolatile memory. A size of the sub-data is smaller than a size of a default transmission unit provided from the host.
Abstract translation: 公开了一种非易失性存储器模块。 非易失性存储器模块包括至少一个非易失性存储器，随机存取存储器（RAM）和器件控制器。 响应于从主机接收到包含子数据的写入请求，设备控制器将该子数据累加在RAM中，并将累积的子数据编程在非易失性存储器中。 子数据的大小小于从主机提供的默认传输单元的大小。
-
公开(公告)号：US11226823B2
公开(公告)日：2022-01-18
申请号：US16879120
申请日：2020-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Younho Jeon , Youngjin Cho , Hee Hyun Nam , Hyo-Deok Shin
Abstract: A memory module includes a device controller that communicates with a host device based on a first interface including a first clock signal, a first data signal, and a first data strobe signal and operates in one of a first operation mode or a second operation mode depending on an operation mode control value from the host device, and a memory device that communicates with the device controller based on a second interface including a second data signal and a second data strobe signal. The device controller includes a logic circuit that transmits a predetermined training result value to the host device depending on a training control value from the host device, when a training is performed on a third interface being a virtual interface recognized by the host device in the first operation mode.
-
公开(公告)号：US10789019B2
公开(公告)日：2020-09-29
申请号：US15855840
申请日：2017-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsik Kim , Jinwoo Kim , Hee Hyun Nam , Kyungbo Yang , Ji-Seung Youn , Younggeun Lee
Abstract: A storage device includes a nonvolatile memory and a controller. The controller includes a job manager circuit and a processor. The job manager circuit manages a first-type job associated with the nonvolatile memory, and the processor processes a second-type job associated with the nonvolatile memory. The job manager circuit manages the first-type job without intervention of the processor. The processor provides a management command to the job manager circuit in response to a notification received from the job manager circuit, such that the second-type job is processed.
-
Patent Agency Ranking
公开(公告)号：US10445014B2
公开(公告)日：2019-10-15
申请号：US15676651
申请日：2017-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hee Hyun Nam , Young Sik Kim , Jin Woo Kim , Young Jo Park , Jae Geun Park , Young Jin Cho
IPC: G06F3/06
Abstract: A method of operating a memory controller is provided. The method of operating a memory controller according to an exemplary embodiment of the present inventive concepts includes sequentially receiving, by the memory controller, first data segments each having a first size from a host, sequentially storing, by the memory controller, the first data segments in the buffer until a sum of sizes of changed data among data stored in a buffer included in the memory controller is a second size, and programming, by the memory controller, the changed data having the second size in a memory space of a non-volatile memory as a second data segment.
-
公开(公告)号：US11742046B2
公开(公告)日：2023-08-29
申请号：US17318234
申请日：2021-05-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeongho Lee , Kwangjin Lee , Hee Hyun Nam , Jaeho Shin , Youngkwang Yoo
CPC classification number: G11C29/42 , G11C7/1012 , G11C7/1063 , G11C29/18 , G11C29/44
Abstract: Disclosed is a method of performing, at a controller, an access to a memory device, which includes transmitting, at the controller, a first command signal, a first address signal, and a first swizzling signal to the memory device, selecting first data bits stored in a memory cell array of the memory device based on the first command signal and the first address signal, and sequentially outputting, at the memory device, at least a part of the first data bits to the controller in a burst manner, based on the first swizzling signal.
-
公开(公告)号：US10929064B2
公开(公告)日：2021-02-23
申请号：US16443551
申请日：2019-06-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngjin Cho , Hee Hyun Nam , Hyo-Deok Shin , Junghwan Ryu
Abstract: An operational method of a memory module is provided. The method includes receiving, from an external of the memory module, a first command and a first address in synchronization with clock signals. Status information is output through a signal line, when first data corresponding the first address is available in a data buffer in response to the first command. A second command in synchronization with the clock signals after the transmitting the status information is received from the external of the memory module, a second command. In response to the second command, the first data being available in the data buffer is output through data lines.
-
公开(公告)号：US10698781B2
公开(公告)日：2020-06-30
申请号：US15996482
申请日：2018-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hee Hyun Nam
Abstract: A semiconductor memory module includes a volatile memory device, a nonvolatile memory device, data buffers, and a controller. The controller outputs first data read from the volatile memory device or the nonvolatile memory device to an external device through the data buffers, and writes second data received from the external device through the data buffers in the volatile memory device or the nonvolatile memory device. The controller performs a failover operation depending on a failover request that includes fail information indicating a position of a failed data buffer among the data buffers. In the failover operation, the controller conveys third data associated with the failed data buffer to the external device through a failover data buffer among the data buffers.
-
公开(公告)号：US20190250834A1
公开(公告)日：2019-08-15
申请号：US16044024
申请日：2018-07-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hee Hyun Nam , Youngjin Cho
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/061 , G06F3/0661 , G06F3/0688
Abstract: The nonvolatile memory module includes at least one nonvolatile memory, and a device controller including a RAM to store data exchanged between a host and the at least one nonvolatile memory and a DIMM controller to control data exchange between the RAM and the at least one nonvolatile memory. An allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data.
-
-
-
-
-
-
-
-
-
Search Results
15
records
(took 0.03 seconds)
