公开(公告)号：US09959935B2

公开(公告)日：2018-05-01

申请号：US15480724

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sukyong Kang ,  Won-Joo Yun ,  Hye-Seung Yu ,  Hyun-Ui Lee ,  Jae-Hun Jung

IPC: G11C29/12 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C29/12 ,  G11C7/1087 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/46 ,  G11C2029/1208

Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.