公开(公告)号：US09142317B2

公开(公告)日：2015-09-22

申请号：US14231856

申请日：2014-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younggeun Lee ,  Youngjin Cho ,  Hyun-Wook Lee ,  Junghyo Woo

IPC: G11C7/00 ,  G11C17/16 ,  G11C17/00 ,  G11C11/00 ,  G06F12/06 ,  G06F13/16

CPC classification number: G11C17/16 ,  G06F12/06 ,  G06F13/1668 ,  G06F13/1694 ,  G11C11/005 ,  G11C17/00 ,  G11C29/822 ,  G11C29/846

Abstract: An embedded memory device includes a mask ROM including a plurality of mask ROM cells and an address decoder configured to decode an address of the plurality of mask ROM cells; and an e-fuse memory configured to replace a part of data stored in the mask ROM with replacement data, the e-fuse memory including, a plurality of e-fuse memory cells configured to store the replacement data, and an e-fuse address selector configured to decode an address of the plurality of e-fuse memory cells and to selectively cause data of one or more of the plurality of e-fuse memory cells to be output based on the decoding result.

Abstract translation: 一种嵌入式存储器件包括：掩模ROM，包括多个掩模ROM单元;以及地址解码器，被配置为对多个掩模ROM单元的地址进行解码; 以及电子熔丝存储器，其被配置为用替换数据替换存储在掩模ROM中的一部分数据，所述电子熔丝存储器包括被配置为存储替换数据的多个电子熔丝存储器单元和电子熔丝地址 所述选择器被配置为解码所述多个电子熔丝存储单元的地址，并且基于所述解码结果选择性地引起所述多个电子熔丝存储器单元中的一个或多个的数据的输出。

公开(公告)号：US09741735B2

公开(公告)日：2017-08-22

申请号：US14993485

申请日：2016-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Wook Lee ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Seunghyun Lim

IPC: H01L27/115 ,  H01L29/423 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/4234 ,  H01L29/42348

Abstract: A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.