公开(公告)号：US20240324243A1

公开(公告)日：2024-09-26

申请号：US18473660

申请日：2023-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjae KIM ,  Woojin KIM ,  Junghoon BAK ,  Hyunchul SHIN ,  Hyeonah JO

IPC: H10B61/00 ,  H01L23/522

CPC classification number: H10B61/22 ,  H01L23/5226

Abstract: A semiconductor device includes a plurality of data storage patterns on a substrate, the plurality of data storage patterns spaced apart from each other in a first direction parallel to an upper surface of the substrate, a first upper conductive line on the plurality of data storage patterns, extending in the first direction and connected to the plurality of data storage patterns, a second upper conductive line on the first upper conductive line and extending in the first direction and a plurality of via contacts between the first upper conductive line and the second upper conductive line and spaced apart from each other in the first direction. The plurality of via contacts are arranged to be offset from the plurality of data storage patterns in the first direction.

公开(公告)号：US20190088656A1

公开(公告)日：2019-03-21

申请号：US15959366

申请日：2018-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong Hyun KIM ,  Seung Pil KO ,  Hyunchul SHIN ,  Kilho LEE

IPC: H01L27/105 ,  G11C11/16 ,  H01L43/02

Abstract: Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.