中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

34 records (took 0.023 seconds)

    Semiconductor memory devices and methods of operating semiconductor memory devices
    1.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US12148494B2

    公开(公告)日：2024-11-19

    申请号：US18115132

    申请日：2023-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyung-Soo Ha

    IPC: G11C29/42 ,  G11C11/406 ,  G11C29/20 ,  G11C29/44

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    2.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US12136463B2

    公开(公告)日：2024-11-05

    申请号：US18113702

    申请日：2023-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyungsoo Ha

    IPC: G11C29/00 ,  G11C29/20 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    5.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11615861B2

    公开(公告)日：2023-03-28

    申请号：US17374822

    申请日：2021-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyungsoo Ha

    IPC: G11C29/00 ,  G11C29/42 ,  G11C29/20 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

    CHIP BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE APPARATUS
    6.
    发明申请
    CHIP BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE APPARATUS 有权

    公开(公告)号：US20210398935A1

    公开(公告)日：2021-12-23

    申请号：US17166805

    申请日：2021-02-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junhyung Kim ,  Joongha Lee ,  Sangha Park ,  Sunghyup Kim ,  Kyeongbin Lim

    IPC: H01L23/00

    Abstract: A chip bonding apparatus includes: a bonding contact configured to apply a bonding force to a semiconductor chip disposed on a substrate, the bonding contact having a first surface configured to face the semiconductor chip and a second surface opposite the first surface, the bonding contact including a protruding portion on the first surface, the protruding portion configured to contact the semiconductor chip, the bonding contact including a cavity formed in a region vertically overlapping the protruding portion, a heater disposed to be in contact with the second surface of the bonding contact to cover the cavity, and configured to heat the bonding contact, a bonding head disposed above the heater and configured to transmit the bonding force, and a partition wall structure protruding from a bottom surface of the cavity to partition an inner space of the cavity.

    SUBSTRATE SUPPORT DEVICE
    8.
    发明公开
    SUBSTRATE SUPPORT DEVICE 审中-公开

    公开(公告)号：US20240318314A1

    公开(公告)日：2024-09-26

    申请号：US18609067

    申请日：2024-03-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yonjoo KANG ,  Yunjae Lee ,  Junhyung Kim ,  Youngbok Lee ,  Sangchul Han ,  Minsung Kim ,  Inhwan Park ,  Sangyeon Oh

    IPC: C23C16/458 ,  C23C16/46

    CPC classification number: C23C16/4586 ,  C23C16/46

    Abstract: A substrate support device includes a chuck plate, a shaft connected to a center lower end of the chuck plate, a heater unit provided inside the chuck plate, an electrode unit provided inside the chuck plate, and provided on the heater unit, a jumper unit provided inside the chuck plate, arranged between the electrode unit and the heater unit, and electrically connected to the electrode unit to supply power to the electrode unit, and a power control unit, wherein the electrode unit includes a center electrode and a first electrode arranged in a ring shape around the center electrode, wherein the jumper unit includes a first jumper connected to the first electrode and a center jumper connected to the center electrode, and wherein the first jumper includes a first connection jumper, and a first inclined jumper electrically connecting the first jumper.

    Semiconductor memory device and a method of operating the semiconductor memory device
    10.
    发明授权
    Semiconductor memory device and a method of operating the semiconductor memory device 有权

    公开(公告)号：US11545211B2

    公开(公告)日：2023-01-03

    申请号：US17400585

    申请日：2021-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiheung Kim ,  Junhyung Kim ,  Sungchul Park ,  Hangyun Jung ,  Hyojin Jung ,  Kyungsoo Ha

    IPC: G11C11/4091 ,  G11C11/408 ,  G06F7/58 ,  G11C11/402

    Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier circuit and a random code generator. The memory cell array is divided into a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction. The sense amplifier circuit is arranged in the second direction with respect to the memory cell array, and includes a plurality of input/output (I/O) sense amplifiers. The random code generator generates a random code which is randomly determined based on a power stabilizing signal and an anti-fuse flag signal. A second group of I/O sense amplifiers selected from among a first group of I/O sense amplifiers performs a data I/O operation by data scrambling data bits of main data. The first group of I/O sense amplifiers correspond to a first group of sub array blocks accessed by an access address.

Patent Agency Ranking