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    Semiconductor memory device and memory system including the same
    1.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US11955159B2

    公开(公告)日：2024-04-09

    申请号：US17703049

    申请日：2022-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong Cho ,  Kiheung Kim ,  Hyeran Kim

    IPC: G11C11/406 ,  G11C11/408 ,  H01L25/065 ,  H03M13/00 ,  H03M13/11

    CPC classification number: G11C11/40615 ,  G11C11/4085 ,  H03M13/1105 ,  H03M13/611 ,  H01L25/0657 ,  H01L2225/06541

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240028221A1

    公开(公告)日：2024-01-25

    申请号：US18302276

    申请日：2023-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungho Lee ,  Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Hyongryol Hwang

    IPC: G06F3/06

    CPC classification number: G06F3/0623 ,  G06F3/0653 ,  G06F3/0673

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    4.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11626181B2

    公开(公告)日：2023-04-11

    申请号：US17245075

    申请日：2021-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyung-Soo Ha

    IPC: G11C29/42 ,  G11C11/406 ,  G11C29/20 ,  G11C29/44

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

    Semiconductor memory device and memory system including the same
    5.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US12236997B2

    公开(公告)日：2025-02-25

    申请号：US18357204

    申请日：2023-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyungho Lee ,  Hyongryol Hwang

    IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20240411467A1

    公开(公告)日：2024-12-12

    申请号：US18811955

    申请日：2024-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongcheol Kim ,  Kiheung Kim ,  Taeyoung Oh ,  Kyungho Lee

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.

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