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    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM
    1.
    发明申请
    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM 有权

    公开(公告)号：US20220068331A1

    公开(公告)日：2022-03-03

    申请号：US17230403

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mingyu LEE ,  Jaewoo PARK ,  Younghoon SON ,  Youngdon CHOI ,  Hyungmin JIN ,  Junghwan CHOI

    IPC: G11C7/22 ,  G11C7/06 ,  G06F13/16

    Abstract: A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20220121582A1

    公开(公告)日：2022-04-21

    申请号：US17326513

    申请日：2021-05-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20220414032A1

    公开(公告)日：2022-12-29

    申请号：US17903240

    申请日：2022-09-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    5.
    发明申请
    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20240370386A1

    公开(公告)日：2024-11-07

    申请号：US18772354

    申请日：2024-07-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

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