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公开(公告)号:US20230352421A1
公开(公告)日:2023-11-02
申请号:US18094786
申请日:2023-01-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sungsik PARK , Jeonghyun KIM , Jonghwa BAEK , Hyunju SONG , Bumjoon YOUN
IPC: H01L23/544 , H01L27/088
CPC classification number: H01L23/544 , H01L27/088 , H01L2223/54426 , H01L29/66439
Abstract: A semiconductor device includes a substrate including a key region, a dummy active pattern provided on the key region, a dummy channel pattern provided on the dummy active pattern, the dummy channel pattern including a first plurality of semiconductor patterns spaced apart from each other, an epitaxial pattern connected to the dummy channel pattern, and a first sub-key pattern provided on the dummy channel pattern. The first sub-key pattern encloses a top surface, a bottom surface, and side surfaces of each of the first plurality of semiconductor patterns.
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公开(公告)号:US20250140711A1
公开(公告)日:2025-05-01
申请号:US18816266
申请日:2024-08-27
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byounghoon KIM , Jihwan SEO , Sangsu JEONG , Sungsik PARK , Giseok SONG , Hyunju SONG
IPC: H01L23/544 , H01L23/528 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/786
Abstract: A semiconductor device may include a substrate including a logic cell region and a key region, an active pattern in the logic cell region, a channel pattern on the active pattern, a plurality of gate electrodes extending on the channel pattern in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, a device separation layer on the key region, and a first key pattern corresponding to the plurality of gate electrodes on the device separation layer.
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公开(公告)号:US20240313049A1
公开(公告)日:2024-09-19
申请号:US18394926
申请日:2023-12-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byounghoon KIM , Hyunwoong KIM , Sungsik PARK , Jonghwa BAEK , KyungMin SUH , Hyunju SONG , Myoungki JUNG
IPC: H01L29/06 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC classification number: H01L29/0673 , H01L27/092 , H01L29/41733 , H01L29/42392 , H01L29/6656 , H01L29/775 , H01L29/78696
Abstract: A semiconductor device includes a substrate having a key region therein, a device isolation layer on the key region, first key patterns on the device isolation layer, and a dummy key pattern extending between the first key patterns, which are adjacent to each other. The first key patterns include a plurality of first sub-key patterns, and the dummy key pattern includes a separation structure, which extends into the device isolation layer and through at least one of the plurality of first sub-key patterns. A first pitch between the plurality of first sub-key patterns may be substantially the same as a second pitch between the separation structure and one of the plurality of first sub-key patterns adjacent thereto.
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公开(公告)号:US20230375936A1
公开(公告)日:2023-11-23
申请号:US18153568
申请日:2023-01-12
Applicant: Samsung Electronics Co, Ltd.
Inventor: Sangjin KIM , Chansik KIM , Geun Su LEE , Sungjae JUNG , Dokyeong KWON , Yigwon KIM , Hyunju SONG , Hyungju RYU , Tae Min CHOI , Keon HUH
IPC: G03F7/32 , C08F297/02
CPC classification number: G03F7/322 , C08F297/02
Abstract: A developing composition and a method of forming a pattern using the same are provided. According to embodiments of inventive concepts, the developing composition may include at least one repeating unit selected from a first repeating unit represented by Chemical Formula A1 a second repeating unit represented by Chemical Formula A2, or both the first repeating unit represented by Chemical Formula A1 and second repeating unit represented by Chemical Formula A2. The developing composition may further include a copolymer including a third repeating unit represented by Chemical Formula A3.
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