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公开(公告)号：US12033551B2
公开(公告)日：2024-07-09
申请号：US18212981
申请日：2023-06-22
发明人： Yilho Lee , Yongil Kwon , Sugyeung Kang , Tae-Hyeon Kwon , Sunkwon Kim , Hyunsang Park , Uijong Song
CPC分类号： G09G3/006 , G09G3/32 , G09G2330/12
摘要： Disclosed is integrated circuit panel which detects fault of a driving circuit. The integrated circuit panel includes: a driving circuit array including first and second driving circuits; a data driver configured to output first and second input data signals through first and second data lines, respectively; a switch driver configured to output a switching signal through a switch line; and an error detection driver configured to receive first and second output data signals through first and second test lines, respectively, wherein, in response to the switching signal, the first and second driving circuits are configured to output the first and second output data signals, which are based on the first and second input data signal, through the first and second test lines, respectively, and the error detection driver is configured to detect a fault of the first or second driving circuit based on the first or second output data signal.
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2.发明授权公开(公告)号：US11949652B2
公开(公告)日：2024-04-02
申请号：US17677220
申请日：2022-02-22
发明人： Sungki Suh , Hyunsang Park , Milim Lee
IPC分类号： H04L61/5007 , H04L61/5053 , H04L101/622 , H04L101/659
CPC分类号： H04L61/5007 , H04L61/5053 , H04L2101/622 , H04L2101/659
摘要： An electronic device and method are disclosed. The electronic device includes memory storing identification of at least an external electronic device, to which an IPv6-based IP address is allocatable, a communication circuit, and a processor. The processor implements the method, including: receiving, from the external electronic device, a router solicitation including a link local address generated by the external electronic device, and identification information of the external electronic device, confirming whether the identification information of the external electronic device included in the router solicitation is stored in the memory, and if so, transmitting a router advertisement including information related to generation of the IP address to the external electronic device.
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公开(公告)号：US11942024B2
公开(公告)日：2024-03-26
申请号：US17748380
申请日：2022-05-19
发明人： Yilho Lee , Yongil Kwon , Sugyeung Kang , Taehyeon Kwon , Kangjoo Kim , Sunkwon Kim , Hyunsang Park
CPC分类号： G09G3/32 , G09G3/035 , G09G3/2088 , G09G3/28 , G09G3/30 , G09G3/3208 , G09G3/3611 , G09G2300/0857 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08 , G09G2330/08
摘要： A display device includes: a cell matrix including a first cell line and a second cell line, wherein the first cell line includes first cells sharing first row lines, and the second cell line includes second cells sharing second row lines; a redundancy integrated circuit including a redundancy cell line including redundancy cells, wherein the redundancy cells share a third row line and are connected to the first and second cells through a plurality of column lines and a plurality of connection lines; and a display driver integrated circuit (DDI) configured to replace the first cell line or the second cell line with the redundancy cell line through the first row lines, the second row lines, and the third row line based on whether the first and second cell lines include a bad cell.
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公开(公告)号：US11895571B2
公开(公告)日：2024-02-06
申请号：US17701451
申请日：2022-03-22
发明人： Jaewon Jang , Ansik Shin , Hyunsang Park , Sungki Suh , Milim Lee , Wonbo Lee
摘要： According to various embodiments, an electronic device may comprise: at least one processor and at least one communication processor. The at least one processor may be configured to: obtain a user equipment (UE) route selection policy (URSP) rule including a first traffic descriptor including a first IP address and a first route selection descriptor corresponding to the first traffic descriptor and request the at least one communication processor to establish a first PDU session corresponding to the first route selection descriptor. The at least one communication processor may be configured to: establish the first PDU session corresponding to the first route selection descriptor in response to the request to establish the first PDU session. A first network interface corresponding to the first PDU session may be established between the at least one communication processor and the at least one processor. The at least one processor may be configured to identify transmission data from an application executed by the at least one processor, request the at least one communication processor to transmit a first transmission packet including a first source IP address corresponding to the first network interface and the transmission data, through the first network interface, based on a destination IP address corresponding to the transmission data corresponding to the first IP address, and request the at least one communication processor to transmit a second transmission packet including a second source IP address corresponding to a second network interface, different from the first network interface, and the transmission data, through the second network interface, based on the destination IP address corresponding to the transmission data not corresponding to the first IP address.
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公开(公告)号：US09754521B2
公开(公告)日：2017-09-05
申请号：US14152144
申请日：2014-01-10
发明人： Seong-Young Ryu , Hyunsang Park , Sungpil Choi
CPC分类号： G09G3/20 , G09G2310/0275 , G09G2310/08 , G09G2330/022
摘要： A display driving circuit in accordance with the inventive concepts may include a source amplifier. The source amplifier may include an output transistor configured to amplify an input signal to generate an output signal, and charge a source line of a display panel using the output signal. The source amplifier may include an output transistor switch configured to control the output transistor, and a switch control block configured to receive configuration bits including on/off time information of the output transistor switch to generate a switch control signal. The on/off time information includes information for turning on the output transistor switch in synchronization with a horizontal synchronous signal associated with the display panel, and information for turning off the output transistor switch at a time when the source line of the display panel is charged to a desired charge level.
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公开(公告)号：US12073773B2
公开(公告)日：2024-08-27
申请号：US17520890
申请日：2021-11-08
发明人： Taehyeon Kwon , Yongil Kwon , Sugyeung Kang , Kangjoo Kim , Sunkwon Kim , Hyunsang Park , Yilho Lee
IPC分类号： G09G3/32
CPC分类号： G09G3/32 , G09G2300/0842 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
摘要： A device includes a pixel array, a row driver configured to, generate a plurality of control signals, drive a plurality of rows of the pixel array using the plurality of control signals, and generate a plurality of clock signals, a row multiplexer configured to receive the plurality of clock signals, and transmit one clock signal of the plurality of clock signals, a data driver configured to transmit a plurality of data signals to the pixel array by column units, each pixel of the plurality of pixels includes, a light emitting device, a shift register configured to receive the selectively transmitted clock signal from the row multiplexer, and generate a width adjusted pulse width modulation (PWM) signal based on a desired brightness level of the light emitting device, and a transistor configured to transmit a driving current to the light emitting device based on the PWM signal.
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公开(公告)号：US11715399B2
公开(公告)日：2023-08-01
申请号：US17701065
申请日：2022-03-22
发明人： Yilho Lee , Yongil Kwon , Sugyeung Kang , Tae-Hyeon Kwon , Sunkwon Kim , Hyunsang Park , Uijong Song
CPC分类号： G09G3/006 , G09G3/32 , G09G2330/12
摘要： Disclosed is integrated circuit panel which detects fault of a driving circuit. The integrated circuit panel includes: a driving circuit array including first and second driving circuits; a data driver configured to output first and second input data signals through first and second data lines, respectively; a switch driver configured to output a switching signal through a switch line; and an error detection driver configured to receive first and second output data signals through first and second test lines, respectively, wherein, in response to the switching signal, the first and second driving circuits are configured to output the first and second output data signals, which are based on the first and second input data signal, through the first and second test lines, respectively, and the error detection driver is configured to detect a fault of the first or second driving circuit based on the first or second output data signal.
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公开(公告)号：US11662770B2
公开(公告)日：2023-05-30
申请号：US17021254
申请日：2020-09-15
发明人： Kyungsoo Lee , Hyunsang Park
CPC分类号： G06F1/1616 , G06F1/1681 , G09G3/2092
摘要： A foldable electronic device includes a first sub-device, a second sub-device, a first hinge connected with the first and second sub-devices, and a single display panel coupled to the first and second sub-devices; where the single display panel includes a main area formed on inner surfaces of the first and second sub-devices, a cover area formed on a first outer surface of the first sub-device, and a round-edge area placed on a first side surface of the first sub-device, and configured to connect the main area and the cover area; where, in a folded state of the foldable electronic device, first information is displayed through the cover area or the round-edge area; and, in an unfolded state of the foldable electronic device, second information is displayed through the main area or the round-edge area.
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公开(公告)号：US20220322199A1
公开(公告)日：2022-10-06
申请号：US17701451
申请日：2022-03-22
发明人： Jaewon Jang , Ansik Shin , Hyunsang Park , Sungki Suh , Milim Lee , Wonbo Lee
摘要： According to various embodiments, an electronic device may comprise: at least one processor and at least one communication processor. The at least one processor may be configured to: obtain a user equipment (UE) route selection policy (URSP) rule including a first traffic descriptor including a first IP address and a first route selection descriptor corresponding to the first traffic descriptor and request the at least one communication processor to establish a first PDU session corresponding to the first route selection descriptor. The at least one communication processor may be configured to: establish the first PDU session corresponding to the first route selection descriptor in response to the request to establish the first PDU session. A first network interface corresponding to the first PDU session may be established between the at least one communication processor and the at least one processor. The at least one processor may be configured to identify transmission data from an application executed by the at least one processor, request the at least one communication processor to transmit a first transmission packet including a first source IP address corresponding to the first network interface and the transmission data, through the first network interface, based on a destination IP address corresponding to the transmission data corresponding to the first IP address, and request the at least one communication processor to transmit a second transmission packet including a second source IP address corresponding to a second network interface, different from the first network interface, and the transmission data, through the second network interface, based on the destination IP address corresponding to the transmission data not corresponding to the first IP address.
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公开(公告)号：US10186219B2
公开(公告)日：2019-01-22
申请号：US15187920
申请日：2016-06-21
发明人： Yong-Hun Kim , Hyunsang Park , Kyungchun Kim , Jae-Bum Lee
摘要： A digital-to-analog converter includes an amplifier including at least two input terminals corresponding to a non-inverting input terminal; and a chopping unit performing a chopping operation between voltages provided to the at least two input terminals corresponding to the non-inverting input terminal. The digital-to-analog converter has an X+Y bit structure and removes an offset by performing an interpolation chopping operation and/or a main buffer chopping operation at the same time. The digital-to-analog structure can be embodied in a small area and can process high bit image data.
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