公开(公告)号：US20230126686A1

公开(公告)日：2023-04-27

申请号：US17871449

申请日：2022-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inhyo Hwang ,  Younglyong Kim ,  Hyunsoo Chung

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate and a plurality of sub-packages provided on the package substrate. Each of the plurality of sub-packages includes a semiconductor chip, an interposer provided adjacent to the semiconductor chip, the interposer including a plurality of first through-silicon vias, an encapsulator provided between the semiconductor chip and the interposer, and a redistribution layer provided on the interposer, the encapsulator and the semiconductor chip. The semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite the first surface and a plurality of chip pads provided on the first surface. The redistribution layer includes a plurality of redistribution pads and a horizontal wiring provided between the plurality of redistribution pads and the plurality of first through-silicon vias. The redistribution layer is provided on the second surface of the semiconductor substrate, and extends on the encapsulator and the interposer.

公开(公告)号：US12159858B2

公开(公告)日：2024-12-03

申请号：US17568361

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Young Lyong Kim ,  Inhyo Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.

公开(公告)号：US20240032311A1

公开(公告)日：2024-01-25

申请号：US18180188

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Young Lyong Kim ,  Inhyo Hwang

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device includes a peripheral circuit structure including peripheral circuits on a substrate and first bonding pads electrically connected to the peripheral circuits and a cell array structure including memory cells on a semiconductor layer and second bonding pads electrically connected to the memory cells and bonded to the first bonding pads. The cell array structure includes a stacked structure including insulating layers and electrodes, an external connection pad on a surface of the semiconductor layer, a dummy pattern at a same level as the semiconductor layer relative to the substrate, and a photosensitive insulating layer on the semiconductor layer and the dummy pattern. A first thickness of a portion of the photosensitive insulating layer vertically overlapping the external connection pad is greater than a second thickness of another portion of the photosensitive insulating layer vertically overlapping the dummy pattern.

公开(公告)号：US20230163090A1

公开(公告)日：2023-05-25

申请号：US18048606

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Inhyo Hwang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device is provided. The memory device includes a first structure and a second structure stacked on the first structure in a vertical direction. The first structure includes a first substrate, peripheral circuitry, an auxiliary memory cell array, a first insulating layer, and a plurality of first bonding pads. The second structure includes a second substrate, a main memory cell array, a second insulating layer, and a plurality of second bonding pads. The plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively.

公开(公告)号：US20250054915A1

公开(公告)日：2025-02-13

申请号：US18930667

申请日：2024-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Young Lyong Kim ,  Inhyo Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.

公开(公告)号：US12218100B2

公开(公告)日：2025-02-04

申请号：US17680617

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyo Hwang ,  Young Lyong Kim

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

Abstract: Provided is a semiconductor package including a first semiconductor chip provided on a package substrate, an interconnection substrate provided on the package substrate, the interconnection substrate having a side surface facing the first semiconductor chip, and a second semiconductor chip provided on the interconnection substrate and extended to a region on a top surface of the first semiconductor chip, wherein the interconnection substrate includes a lower interconnection layer facing the package substrate, an upper interconnection layer facing the first semiconductor chip, and a passive device between the lower interconnection layer and the upper interconnection layer, and wherein the passive device is electrically connected to the second semiconductor chip.

公开(公告)号：US12033948B2

公开(公告)日：2024-07-09

申请号：US17539963

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim ,  Hyunsoo Chung ,  Inhyo Hwang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/3114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.

公开(公告)号：US20250046749A1

公开(公告)日：2025-02-06

申请号：US18783805

申请日：2024-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Kwangsoo Kim ,  Inhyo Hwang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes an interposer; a plurality of semiconductor devices that are on the interposer and spaced apart from each other; and a package underfill layer that includes a first underfill layer in a first gap that is between the plurality of semiconductor devices and a second underfill layer in a second gap that is between the plurality of semiconductor devices and the interposer, where the second underfill layer includes a second underfill layer side surface that faces a lateral direction, where the second underfill layer side surface does not contact the plurality of semiconductor devices and a portion of the interposer that is adjacent to the second gap, where the second underfill layer side surface extends between a top surface of the interposer and bottom surfaces of the plurality of semiconductor devices and extends from a lower outer boundary.

公开(公告)号：US20250022843A1

公开(公告)日：2025-01-16

申请号：US18428633

申请日：2024-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Jaesic Lee ,  Inhyo Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L25/00 ,  H01L25/18

Abstract: Provided a semiconductor package including a redistribution structure, a semiconductor structure on the redistribution structure, a plurality of semiconductor stacking structures on the redistribution structure, the plurality of semiconductor stacking structures being adjacent to the semiconductor structure, and a height of each of the plurality of semiconductor stacking structures being greater than a height of the semiconductor structure, and a heat dissipation structure on the semiconductor structure, the heat dissipation structure including a plurality of through openings, wherein each semiconductor stacking structure among the plurality of semiconductor stacking structures is positioned within a corresponding through opening among the plurality of through openings, and wherein an upper surface of each of the plurality of semiconductor stacking structures is exposed through the corresponding through opening.

公开(公告)号：US20240332200A1

公开(公告)日：2024-10-03

申请号：US18737527

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim ,  Hyunsoo Chung ,  Inhyo Hwang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/3114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.