公开(公告)号：US20190333823A1

公开(公告)日：2019-10-31

申请号：US16503728

申请日：2019-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk LEE ,  JEONGYUN LEE ,  Yongseok LEE ,  Bosoon KIM ,  SANGDUK PARK ,  Seungchul OH ,  YOUNGMOOK OH

IPC: H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L21/762

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20220122891A1

公开(公告)日：2022-04-21

申请号：US17562802

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk LEE ,  JEONGYUN LEE ,  Yongseok LEE ,  Bosoon KIM ,  SANGDUK PARK ,  Seungchul OH ,  YOUNGMOOK OH

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/08

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20180240881A1

公开(公告)日：2018-08-23

申请号：US15692560

申请日：2017-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNHO JUNG ,  JEONGYUN LEE ,  TAESOON KWON ,  KYUNGSEOK MIN ,  GEUMJUNG SEONG ,  BORA LIM ,  A-REUM JI ,  SEUNGSOO HONG

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/4236 ,  H01L27/0924 ,  H01L29/0653

Abstract: A semiconductor device can include a first active pattern on a substrate, the first active pattern including a plurality of first active regions that protrude from the substrate. A second active pattern can be on the substrate including a plurality of second active regions that protrude from the substrate. A first gate electrode can include an upper portion that extends over the first active pattern at a first height and include a recessed portion that extends over the first active pattern at a second height that is lower than the first height of the first gate electrode. A second gate electrode can include an upper portion that extends over the second active pattern at a first height and include a recessed portion that extends over the second active pattern at a second height that is lower than the first height of the second gate electrode. An insulation pattern can be located between, and directly adjacent to, the recessed portion of the first gate electrode and the recessed portion of the second gate electrode, the insulation pattern electrically isolating the first and second gate electrodes from one another.

公开(公告)号：US20170200651A1

公开(公告)日：2017-07-13

申请号：US15405420

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk LEE ,  JEONGYUN LEE ,  Yongseok LEE ,  Bosoon KIM ,  SANGDUK PARK ,  Seungchul OH ,  YOUNGMOOK OH

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.