公开(公告)号：US20170018553A1

公开(公告)日：2017-01-19

申请号：US15198035

申请日：2016-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Noh LEE ,  YOUNGKUK KIM ,  SANGYEOL KANG ,  JOONSOO PARK ,  KiVin IM

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10888

Abstract: A method for manufacturing a semiconductor device may include forming contact pads spaced apart from each other in a first direction on a substrate and between first insulating patterns; forming first holes between the first insulating patterns and having bottom ends adjacent top surfaces of the contact pads; forming second holes between second insulating patterns and overlapping with partial portions of the first holes in a second direction perpendicular to the first direction; and forming a bottom electrode layer including first portions to cover the bottom ends of the first holes and sidewalls of the second holes. In forming the first and second holes, the first and second holes are formed simultaneously.

Abstract translation: 制造半导体器件的方法可以包括在衬底上沿第一方向和第一绝缘图案之间形成彼此间隔开的接触焊盘; 在所述第一绝缘图案之间形成第一孔并且具有邻近所述接触垫的顶表面的底端; 在第二绝缘图案之间形成第二孔，并在垂直于第一方向的第二方向上与第一孔的部分部分重叠; 以及形成包括第一部分的底部电极层，以覆盖第一孔的底端和第二孔的侧壁。 在形成第一和第二孔时，第一和第二孔同时形成。

公开(公告)号：US20150104946A1

公开(公告)日：2015-04-16

申请号：US14467400

申请日：2014-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JOONSOO PARK ,  Soonmok Ha ,  Eunshoo Han ,  Seongho Moon ,  Sung-Wook Hwang

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/30604 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/10852 ,  H01L27/11551 ,  H01L27/11578

Abstract: Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings.

Abstract translation: 提供了形成用于半导体器件的精细图案的方法。 一种方法可以包括顺序地形成下层和在衬底上具有第一开口的掩模层，形成柱以填充第一开口并从掩模层的顶表面向上突出，在衬底上形成具有柱的嵌段共聚物层 对所述嵌段共聚物层进行热处理以形成第一嵌段部分和第二嵌段部分，除去所述第二嵌段部分以形成暴露所述掩模层的引导开口，以及蚀刻由所述引导开口露出的掩模层以形成第二开口。