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    Layout decomposition methods and systems
    1.
    发明授权
    Layout decomposition methods and systems 有权

    公开(公告)号：US09874810B2

    公开(公告)日：2018-01-23

    申请号：US15135041

    申请日：2016-04-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-Young Jung ,  Dae-Kwon Kang ,  Dong-Gyun Kim ,  Jae-Seok Yang ,  Sung-Wook Hwang

    IPC: G06F17/50 ,  G03F1/70 ,  G03F1/68

    CPC classification number: G03F1/70 ,  G03F1/68

    Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.

    METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICES
    4.
    发明申请
    METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICES 有权
    形成半导体器件精细图案的方法

    公开(公告)号：US20150104946A1

    公开(公告)日：2015-04-16

    申请号：US14467400

    申请日：2014-08-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JOONSOO PARK ,  Soonmok Ha ,  Eunshoo Han ,  Seongho Moon ,  Sung-Wook Hwang

    IPC: H01L21/306 ,  H01L21/311 ,  H01L21/308

    CPC classification number: H01L21/30604 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/10852 ,  H01L27/11551 ,  H01L27/11578

    Abstract: Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings.

    Abstract translation: 提供了形成用于半导体器件的精细图案的方法。 一种方法可以包括顺序地形成下层和在衬底上具有第一开口的掩模层，形成柱以填充第一开口并从掩模层的顶表面向上突出，在衬底上形成具有柱的嵌段共聚物层 对所述嵌段共聚物层进行热处理以形成第一嵌段部分和第二嵌段部分，除去所述第二嵌段部分以形成暴露所述掩模层的引导开口，以及蚀刻由所述引导开口露出的掩模层以形成第二开口。

    Test pattern, test method for semiconductor device, and computer-implemented method for designing integrated circuit layout
    6.
    发明授权
    Test pattern, test method for semiconductor device, and computer-implemented method for designing integrated circuit layout 有权

    公开(公告)号：US10885244B2

    公开(公告)日：2021-01-05

    申请号：US16739624

    申请日：2020-01-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Wook Hwang ,  Jong-Hyun Lee ,  Min-Soo Kang

    IPC: G06F30/30 ,  H01L21/66

    Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.

    Test pattern, test method for semiconductor device, and computer-implemented designing integrated circuit layout
    10.
    发明授权
    Test pattern, test method for semiconductor device, and computer-implemented designing integrated circuit layout 有权

    公开(公告)号：US10572616B2

    公开(公告)日：2020-02-25

    申请号：US15259673

    申请日：2016-09-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Wook Hwang ,  Jong-Hyun Lee ,  Min-Soo Kang

    IPC: G06F17/50 ,  H01L21/66

    Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.

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