公开(公告)号：US20230387889A1

公开(公告)日：2023-11-30

申请号：US18154966

申请日：2023-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunseok NAM ,  Jaehyuk YANG ,  Yongsung CHO

IPC: H03K3/012 ,  H03H11/04 ,  H03F3/387 ,  H03K5/24 ,  G06F1/06

CPC classification number: H03K3/012 ,  H03H11/04 ,  H03F3/387 ,  H03K5/24 ,  G06F1/06 ,  H03K2005/00013

Abstract: A clock generating device includes a first voltage output circuit configured to output a first voltage corresponding to a power supply voltage in response to a preliminary clock signal, a clock output circuit configured to generate the preliminary clock signal and a final clock signal at a period corresponding to a difference between the first voltage and a negative feedback voltage, a negative feedback voltage generating circuited configured to generate the negative feedback voltage from a reference value corresponding to a frequency of the final clock signal and a second voltage and filtered to a uniform voltage level, and a second voltage output circuit configured to output the second voltage to the negative feedback voltage generating unit, the second voltage having lower sensitivity of fluctuations in the power supply voltage than the first voltage.

公开(公告)号：US20230112849A1

公开(公告)日：2023-04-13

申请号：US17881009

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dobin KIM ,  Wontaeck JUNG ,  Jaehyuk YANG ,  Jinwoo YANG

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A memory device and a method for programming the same may include, applying program loops to a plurality of memory cells of the memory device to adjust threshold voltages of the plurality of memory cells to desired target states, each of the program loops including a program section and a verification section, programming the memory cells of a first page, storing a number of first program loops used to complete the programming of the memory cells of the first page to a first target state, programming the memory cells of a second page to the first target state, the second page adjacent to the first page, and performing a verification operation on the second page.