公开(公告)号：US20230043714A1

公开(公告)日：2023-02-09

申请号：US17971807

申请日：2022-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon LEE ,  Munjun KIM ,  Jaekang KOH ,  Tae-Jong HAN

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/3213

Abstract: Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.

公开(公告)号：US20220173002A1

公开(公告)日：2022-06-02

申请号：US17672939

申请日：2022-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungheon LEE ,  Jaekang KOH ,  Hyukwoo KWON ,  Munjun KIM ,  Taejong HAN

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/02

Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.

公开(公告)号：US20240196599A1

公开(公告)日：2024-06-13

申请号：US18512135

申请日：2023-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekang KOH ,  Byeongguk KO ,  Chanyoung KIM ,  Sangkoo NAM ,  Yongsoon CHOI

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315

Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a gate structure disposed on the active pattern; a bit line structure disposed on the active pattern, and including a first conductive pattern, a second conductive pattern and an insulation structure stacked on each other, a lower spacer structure disposed on a sidewall of the bit line structure; an upper spacer structure disposed on the lower spacer structure, wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure; a contact plug structure disposed on the active pattern, wherein the contact plug structure is spaced apart from the bit line structure; and a capacitor disposed on the contact plug structure, wherein the lower spacer structure includes: a first spacer partially covering a sidewall of the first conductive pattern, and including air; and a second spacer disposed on the first spacer.

公开(公告)号：US20210125884A1

公开(公告)日：2021-04-29

申请号：US16919307

申请日：2020-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungheon LEE ,  Jaekang KOH ,  Hyukwoo KWON ,  Munjun KIM ,  Taejong HAN

IPC: H01L23/29 ,  H01L21/02 ,  H01L23/31

Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.