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    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING THE SAME 有权

    公开(公告)号：US20230124660A1

    公开(公告)日：2023-04-20

    申请号：US17938651

    申请日：2022-10-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinhoon Jang ,  Kyungryun Kim

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array and a plurality of data input/output (I/O) pins. The plurality of data I/O pins is configured to receive write data to be stored in the memory cell array or to output read data stored in the memory cell array. The semiconductor memory device is configured to perform a burst operation in which a single data set comprising a plurality of data bits is input or output through the plurality of data I/O pins based on a single command received from an external memory controller. A number of the plurality of data I/O pins corresponds to an integer that is not a power-of-two. A burst length representing a unit of the burst operation corresponds to an integer that is not a power-of-two.

    Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same
    6.
    发明授权
    Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same 有权

    公开(公告)号：US12205668B2

    公开(公告)日：2025-01-21

    申请号：US17722805

    申请日：2022-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaemin Choi ,  Yonghun Kim ,  Jaewoo Jeong ,  Kyungryun Kim ,  Yoochang Sung ,  Changsik Yoo

    IPC: G11C7/10

    Abstract: A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

    Voltage trimming circuit
    7.
    发明授权
    Voltage trimming circuit 有权

    公开(公告)号：US12062404B2

    公开(公告)日：2024-08-13

    申请号：US18239548

    申请日：2023-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minho Choi ,  Jaeseong Lim ,  Kyungryun Kim ,  Daehyun Kim ,  Wonil Bae ,  Hohyun Shin ,  Sanghoon Jung ,  Hyongryol Hwang

    IPC: G11C17/18 ,  G11C17/16 ,  G11C29/08

    CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/08

    Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

    Semiconductor memory device and data path configuration method thereof
    9.
    发明授权
    Semiconductor memory device and data path configuration method thereof 有权

    公开(公告)号：US10553273B2

    公开(公告)日：2020-02-04

    申请号：US16032822

    申请日：2018-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jang-Woo Ryu ,  Kyungryun Kim ,  Soo Hwan Kim ,  Huikap Yang

    IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4097 ,  G11C11/4093

    Abstract: A semiconductor memory device includes a cell array that includes a first row block and a second row block, a bit line sense amplifier block that senses data stored in the first row block or the second row block, a local sense amplifier that latches the sensed data transferred from the bit line sense amplifier block, and a switch that connects the local sense amplifier with a selected one of a first global data line and a second global data line in response to a select signal. The second row block may be placed at an edge of the cell array, and the switch connects the local sense amplifier with the first global data line when the first row block is activated and connects the local sense amplifier with the second global data line when the second row block is activated.

    Memory device, a memory system and an operating method of the memory device
    10.
    发明授权
    Memory device, a memory system and an operating method of the memory device 有权

    公开(公告)号：US12073914B2

    公开(公告)日：2024-08-27

    申请号：US17869061

    申请日：2022-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungryun Kim

    IPC: G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/109 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/22

    Abstract: A memory device includes: a memory bank including a plurality of memory cells; and a memory interface circuit configured to store data in the plurality of memory cells based on a command/address signal and a data signal, wherein the memory interface circuit includes: first, second, third and fourth pads configured to receive first, second, third and fourth clock signals, respectively; a first buffer circuit configured to sample the command/address signal in response to an activation time of the first and third clock signals which have opposite phases from each other; and a second buffer circuit configured to sample the data signal in response to the activation time of the first clock signal, an activation time of the second clock signal, the activation time of the third clock signal and an activation time of the fourth clock signal.

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