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    Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same
    2.
    发明授权
    Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same 有权

    公开(公告)号：US12205668B2

    公开(公告)日：2025-01-21

    申请号：US17722805

    申请日：2022-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaemin Choi ,  Yonghun Kim ,  Jaewoo Jeong ,  Kyungryun Kim ,  Yoochang Sung ,  Changsik Yoo

    IPC: G11C7/10

    Abstract: A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230377667A1

    公开(公告)日：2023-11-23

    申请号：US18319584

    申请日：2023-05-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaewoo Lee ,  Yonghun Kim ,  Kihan Kim ,  ChangSik Yoo

    IPC: G11C29/12 ,  G11C29/36

    CPC classification number: G11C29/12015 ,  G11C29/36 ,  G11C29/1201

    Abstract: A semiconductor device includes: a data clock signal generator circuit configured to output a plurality of data clock signals that have different phases and that are used to generate a plurality of internal data clock signals of a memory device; a data transmitter configured to generate a data signal based on a test pattern transitioned once, delay the data signal once transitioned according to a delay value, and output the data signal to the memory device; a data receiver configured to receive an output signal from the memory device that includes first sampling data, the first sampling data being obtained by sampling the data signal based on a first internal data clock signal from the plurality of internal data clock signals; and a training circuit configured to change the delay value and determine a final value of the delay value based on the first sampling data.

    MEMORY DEVICE AND METHOD FOR TRAINING PER-PIN OPERATION PARAMETERS
    7.
    发明公开
    MEMORY DEVICE AND METHOD FOR TRAINING PER-PIN OPERATION PARAMETERS 审中-公开

    公开(公告)号：US20240212725A1

    公开(公告)日：2024-06-27

    申请号：US18468227

    申请日：2023-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Garam Choi ,  Yonghun Kim ,  Kihan Kim

    IPC: G11C7/10

    CPC classification number: G11C7/1048 ,  G11C2207/2254

    Abstract: Provided are a memory device and a method for training per-pin operation parameters. A memory device includes a plurality of on-die termination (ODT) circuits, an impedance control (ZQ) calibration circuit configured to output a first code signal and a second code signal, and a per-pin calibration circuit. The per-pin calibration circuit may be configured to select one signal pin from among the plurality of signal pins, to compare a first input voltage level of the selected signal pin with a second input voltage level of each of the other ones of the plurality of signal pins, to generate a per-pin ODT code signal for each of the plurality of signal pins, to combine the per-pin ODT code signal with the first code signal or the second code signal, and to provide the combined per-pin ODT code signal to the respective ODT circuits.

    SEMICONDUCTOR DEVICE
    9.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230377621A1

    公开(公告)日：2023-11-23

    申请号：US18189580

    申请日：2023-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaewoo Lee ,  Yonghun Kim ,  Kihan Kim ,  ChangSik Yoo

    IPC: G11C7/22 ,  G11C7/10 ,  G11C29/02

    CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C29/023 ,  G11C7/1093 ,  G11C2207/2254

    Abstract: A semiconductor device includes: a clock generation circuit configured to output a plurality of clock signals that have different phases to a memory device, an internal clock signal of the memory device being generated responsive to the plurality of clock signals; and a training circuit configured to receive an output signal output based on the internal clock signal from the memory device, to adjust a value of a code used to generate the internal clock signal by adjusting the phase of at least one clock signal among the plurality of clock signals, to determine a final value of the code based on a duty cycle of the output signal, which is changed according to the adjustment of the value of the code, and to write the final value to the memory device.

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