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    Electronic device for improving image quality
    1.
    发明授权
    Electronic device for improving image quality 有权

    公开(公告)号：US12149836B2

    公开(公告)日：2024-11-19

    申请号：US18070771

    申请日：2022-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wonjoon Do ,  Woojhon Choi ,  Jaesung Choi

    IPC: H04N23/81 ,  H04N23/71 ,  H04N23/76

    Abstract: An electronic device may include: a camera; a display positioned between an object to be photographed by the camera and the camera; a processor connected to the camera and the display; and a memory operatively connected to the processor, wherein the memory stores instructions that, when executed, cause the processor to: receive an original image from the camera; input the original image as an input value to an artificial intelligence model trained for improving image quality, and obtain a correction image from a result value output from the artificial intelligent model; detect a saturated area in which a light source is depicted in the correction image; and obtain a compensation image by blurring a boundary between the saturated area and a periphery thereof in the correction image by using the original image.

    COLUMN REDUNDANCY CIRCUIT AND MEMORY DEVICE INCLUDING SAME
    3.
    发明申请
    COLUMN REDUNDANCY CIRCUIT AND MEMORY DEVICE INCLUDING SAME 有权

    公开(公告)号：US20250167805A1

    公开(公告)日：2025-05-22

    申请号：US18764731

    申请日：2024-07-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiryong Kim ,  Inhak Lee ,  Jaesung Choi

    IPC: H03M13/09 ,  H03M13/00

    Abstract: An example column redundancy circuit of a memory device comprises a pre-decoder circuit, a main decoder circuit, and a shift logic circuit. The pre-decoder circuit is configured to receive a lower column address from a plurality of fault column addresses and perform a first decoding operation, and to receive an upper column address from the plurality of fault column address and perform a second decoding operation. The main decoder circuit includes a plurality of main decoders, and each main decoder is configured to receive a lower signal and one or more upper signals from the pre-decoder circuit and to perform a main decoding operation. The shift logic circuit includes a plurality of shift logics, and each shift logic is configured to generate a shift signal that performs a column shift operation according to a result of the main decoding operation.

    Static random access memory device
    4.
    发明授权
    Static random access memory device 有权

    公开(公告)号：US11875844B2

    公开(公告)日：2024-01-16

    申请号：US17577198

    申请日：2022-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Inhak Lee ,  Sang-Yeop Baeck ,  Younghwan Park ,  Jaesung Choi

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

    Abstract: Disclosed is a static random access memory (SRAM) device. According to example embodiments of the present disclosure, a control logic of the SRAM device may include a tracking circuit connected with metal lines for tracking the number of columns of a memory cell array and the number of rows of the memory cell array. By the tracking circuit, a length of word lines of the memory cell array and a length of bit lines of the memory cell array may be tracked. The control logic of the SRAM device may generate control pulses optimized for the size of the memory cell array, based on a tracking result(s) of the tracking circuit. Accordingly, a power and a time necessary for a write operation and a read operation may be reduced.

    PULSE GENERATOR AND MEMORY DEVICE COMPRISING THE SAME
    5.
    发明申请
    PULSE GENERATOR AND MEMORY DEVICE COMPRISING THE SAME 有权

    公开(公告)号：US20250046366A1

    公开(公告)日：2025-02-06

    申请号：US18420456

    申请日：2024-01-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiryong KIM ,  Inhak Lee ,  Jaesung Choi

    IPC: G11C11/418 ,  G11C11/419

    Abstract: A memory device includes a cell array including a plurality of static random-access memory (SRAM) cells; a row decoder configured to drive a plurality of word lines of the plurality of SRAM cells based on a row address; a data input/output circuit connected to a plurality of bit lines of the cell array and connected to a sub-power line configured to supply cell voltage to the plurality of SRAM cells; and a word line pulse generator configured to generate a word line pulse with a first pulse width that varies based on the row address and to provide the word line pulse to the row decoder.

    Method for photographing in multiple directions through one camera and electronic device thereof
    9.
    发明授权
    Method for photographing in multiple directions through one camera and electronic device thereof 有权

    公开(公告)号：US12073031B2

    公开(公告)日：2024-08-27

    申请号：US18070763

    申请日：2022-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wonjoon Do ,  Woojhon Choi ,  Jaesung Choi ,  Kihuk Lee

    IPC: G06F3/0354 ,  H04N7/18 ,  H04N19/597

    CPC classification number: G06F3/03545 ,  H04N7/181 ,  H04N19/597

    Abstract: An electronic device is provided. The electronic device includes a housing, the housing including an opening formed on a portion thereof and an internal space extending from the opening into the housing, a first wireless communication circuit, a display including a first area, an electronic pen insertable into the internal space through the opening and including a camera and a second wireless communication circuit, the camera of the electronic pen being positioned at a point corresponding to the first area when the electronic pen is inserted into the internal space of the housing, and at least one processor connected to the first wireless communication circuit, the display and the electronic pen, and configured to obtain image data obtained by the camera included in the electronic pen through the first wireless communication circuit and output the obtained image data through the display.

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