公开(公告)号：US12255094B2

公开(公告)日：2025-03-18

申请号：US17739114

申请日：2022-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyuk Lim ,  Jong Min Baek ,  Deok Young Jung ,  Sung Jin Kang ,  Jang Ho Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234

Abstract: There is provided a semiconductor device including an etching stop film which is placed disposed on a substrate; an interlayer insulating film which is disposed on the etching stop film; a trench which penetrates the interlayer insulating film and the etching stop film; a spacer which extends along side walls of the trench; a barrier film which extends along the spacer and a bottom surface of the trench; and a filling film which fills the trench on the barrier film. The trench includes a first trench and a second trench which are spaced apart from each other in a first direction and have different widths from each other in the first direction. A bottom surface of the second trench is placed disposed below a bottom surface of the first trench.

公开(公告)号：US11881430B2

公开(公告)日：2024-01-23

申请号：US17826366

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin Kang ,  Jong Min Baek ,  Woo Kyung You ,  Kyu-Hee Han ,  Han Seong Kim ,  Jang Ho Lee ,  Sang Shin Jang

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76808 ,  H01L23/481 ,  H01L21/76832

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US10475739B2

公开(公告)日：2019-11-12

申请号：US15840128

申请日：2017-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung You ,  Eui Bok Lee ,  Jong Min Baek ,  Su Hyun Bark ,  Jang Ho Lee ,  Sang Hoon Ahn ,  Hyeok Sang Oh

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.

公开(公告)号：US20230307370A1

公开(公告)日：2023-09-28

申请号：US17968050

申请日：2022-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Ho Lee ,  Woo Kyung You ,  Jong Min Baek

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895

Abstract: A semiconductor device is provided. The semiconductor device includes a first interlayer insulating layer, a lower wiring disposed inside the first interlayer insulating layer, an etching stop layer which includes first to third layers sequentially stacked on the first interlayer insulating layer, a second interlayer insulating layer disposed on the etching stop layer, and a via which penetrates the second interlayer insulating layer and the etching stop layer, the via is connected to the lower wiring, the via includes a first side wall that is in contact with the second layer, and a second side wall that is in contact with the second interlayer insulating layer, the via includes a first protrusion protruding in a horizontal direction from the first side wall inside the first layer, and a second protrusion protruding in the horizontal direction from the first side wall inside the third layer.

公开(公告)号：US11348827B2

公开(公告)日：2022-05-31

申请号：US16798789

申请日：2020-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin Kang ,  Jong Min Baek ,  Woo Kyung You ,  Kyu-Hee Han ,  Han Seong Kim ,  Jang Ho Lee ,  Sang Shin Jang

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US12218002B2

公开(公告)日：2025-02-04

申请号：US18537896

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin Kang ,  Jong Min Baek ,  Woo Kyung You ,  Kyu-Hee Han ,  Han Seong Kim ,  Jang Ho Lee ,  Sang Shin Jang

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.