公开(公告)号：US20190305202A1

公开(公告)日：2019-10-03

申请号：US16356283

申请日：2019-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tan SAKONG ,  Yong Il KIM ,  Han Kyu SEONG ,  Ji Hye YEON ,  Chung Sun LEE ,  Ji Hwan HWANG

IPC: H01L33/62 ,  H01L25/075 ,  H01L27/12 ,  H01L23/00

Abstract: A light emitting diode display device includes a display board comprising a plurality of unit pixels, a drive circuit board including a plurality of drive circuit regions corresponding to the plurality of unit pixels, and a plurality of bumps interposed between the plurality of unit pixels and the plurality of drive circuit regions. The plurality of unit pixels comprises a first unit pixel including a first P electrode. The plurality of drive circuit regions comprises a first drive circuit region corresponding to the first unit pixel and a first pad connected to a first drive transistor, the plurality of bumps includes a first solder in contact with the first pad, and a first bump on the first solder and including a first filler in contact with the first P electrode, the first solder includes at least one of tin and silver, and the first filler includes copper or nickel.

公开(公告)号：US20210225796A1

公开(公告)日：2021-07-22

申请号：US17221304

申请日：2021-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Chul KIM ,  Tae Hun KIM ,  Ji Hwan HWANG

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/18

Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.

公开(公告)号：US20200098719A1

公开(公告)日：2020-03-26

申请号：US16438505

申请日：2019-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Sick PARK ,  Un Byoung KANG ,  Tae Hong MIN ,  Teak Hoon LEE ,  Ji Hwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.

公开(公告)号：US20220028837A1

公开(公告)日：2022-01-27

申请号：US17493975

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwan HWANG ,  Ji Hoon KIM ,  Ji Seok HONG ,  Tae Hun KIM ,  Hyuek Jae LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.