公开(公告)号：US20130087929A1

公开(公告)日：2013-04-11

申请号：US13690678

申请日：2012-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Man KIM ,  In-Ku KANG ,  Ji-Hyun LEE

IPC: H01L23/49

CPC classification number: H01L23/49 ,  H01L23/3128 ,  H01L24/00 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/4911 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided are semiconductor packages and electronic systems including the same. A first memory chip may be stacked on a first portion of a substrate. A controller chip may be stacked on a second portion of the substrate, which is different from the first portion. At least one first bonding wire may directly connect the first memory chip with the controller chip. At least one second bonding wire may directly connect the first memory chip with the substrate, and may be electrically connected with the at least one first bonding wire.

Abstract translation: 提供半导体封装和包括其的电子系统。 第一存储器芯片可以堆叠在衬底的第一部分上。 控制器芯片可以堆叠在与第一部分不同的基板的第二部分上。 至少一个第一接合线可以将第一存储器芯片与控制器芯片直接连接。 至少一个第二接合线可以将第一存储器芯片与衬底直接连接，并且可以与至少一个第一接合线电连接。

公开(公告)号：US20140198589A1

公开(公告)日：2014-07-17

申请号：US14147545

申请日：2014-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Il MOK ,  Jong-Hyoung LIM ,  Dae-Sun KIM ,  Ji-Hyun LEE

IPC: G11C7/06

CPC classification number: G11C11/4076 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

Abstract: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.

Abstract translation: 半导体器件可以包括连接到位线和第一字线的第一存储器单元，连接到互补位线和第二字线的第二存储器单元以及均衡器。 均衡器可以被配置为当位线和互补位线浮置时在第一时间段将位线和互补位线的电压从第一电压转换到不同于第一电压的第二电压， 并且当所述位线和互补位线浮置时，在所述第一时间段之后的第二时间周期将所述位线和所述互补位线中的至少一个的电压从所述第二电压转换到第三电压， 第三电压与第一和第二电压不同。