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公开(公告)号：US11658148B2
公开(公告)日：2023-05-23
申请号：US16854452
申请日：2020-04-21
发明人： Hyuekjae Lee , Jihoon Kim , JiHwan Suh , So Youn Lee , Jihwan Hwang , Taehun Kim , Ji-Seok Hong
IPC分类号： H01L25/00 , H01L25/065 , H01L23/00 , H01L25/18 , H01L21/56
CPC分类号： H01L25/0652 , H01L21/565 , H01L24/08 , H01L24/80 , H01L25/18 , H01L25/50 , H01L2224/08146 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06555 , H01L2225/06586 , H01L2225/06589
摘要： A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.
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公开(公告)号：US12040313B2
公开(公告)日：2024-07-16
申请号：US18133959
申请日：2023-04-12
发明人： Hyuekjae Lee , Jihoon Kim , JiHwan Suh , So Youn Lee , Jihwan Hwang , Taehun Kim , Ji-Seok Hong
CPC分类号： H01L25/0652 , H01L21/565 , H01L24/08 , H01L24/80 , H01L25/18 , H01L25/50 , H01L2224/08146 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06555 , H01L2225/06586 , H01L2225/06589
摘要： A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.
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