公开(公告)号：US11095121B2

公开(公告)日：2021-08-17

申请号：US16432962

申请日：2019-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Ho Jeon ,  Jin-Hee Park ,  Hyuck-Joon Kwon

IPC: H02H9/04 ,  H03K3/3565 ,  H02H1/00

Abstract: An electrostatic protection circuit with variable Schmitt trigger characteristics is provided. The electrostatic protection circuit uses a Schmitt trigger circuit to protect an integrated circuit against an overvoltage. The Schmitt trigger circuit includes first and second branches bridged between a power supply rail and a ground rail. The Schmitt trigger circuit operates with a narrow hysteresis width when the second branch is connected in parallel to the first branch and with a wide hysteresis width when the second branch is not connected in parallel to the first branch. The electrostatic protection circuit discharges an overvoltage of the power supply rail using a narrow hysteresis width when a weak overvoltage is applied to the power supply rail, and discharges an overvoltage of the power supply rail using a wide hysteresis width when a strong overvoltage is applied to the power supply rail.

公开(公告)号：USD776142S1

公开(公告)日：2017-01-10

申请号：US29497837

申请日：2014-07-29

Applicant: Samsung Electronics Co., Ltd.

Designer： Ji-Hye Kim ,  Ji-Yoon Lee ,  Eun-Bi Kim ,  Jin-Hee Park ,  Ja-Youn Lee

公开(公告)号：US09118313B2

公开(公告)日：2015-08-25

申请号：US14466509

申请日：2014-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Lee ,  Jin-Hee Park

IPC: G11C11/00 ,  H03K19/00 ,  G11C7/12

CPC classification number: H03K19/0005 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/12 ,  G11C2207/2254

Abstract: Provided is a semiconductor memory device calibrating a termination resistance, the semiconductor memory device comprising self-adjustment logic configured to determine whether a value of an upper bit string of a calibration code generated in response to a calibration start signal is equal to or greater than an upper critical value of the calibration code, or is equal to or less than a lower critical value of the calibration code, and to generate an adjustment signal for adjusting a value of a termination resistance of a data output driver based on the determination result; and resistance calibration logic configured to provide the upper bit string to the self-adjustment logic, and to generate an updated calibration code by performing a calibration calculation based on the calibration code and a comparison signal generated according to a result of comparing a reference voltage and a voltage of a comparison target node.

Abstract translation: 提供了校准端接电阻的半导体存储器件，所述半导体存储器件包括自调整逻辑，其被配置为确定响应于校准开始信号产生的校准代码的高位位串的值是否等于或大于 校准代码的上临界值或者等于或小于校准代码的较低临界值，并且基于确定结果生成用于调整数据输出驱动器的终端电阻的值的调整信号; 以及电阻校准逻辑，被配置为将所述高位串提供给所述自调节逻辑，并且通过基于所述校准代码执行校准计算以及根据比较参考电压和 比较目标节点的电压。