公开(公告)号：US10725682B2

公开(公告)日：2020-07-28

申请号：US16103078

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wang-Soo Kim ,  Jung-Hwan Choi ,  Ki-Duk Park ,  Yoo-Chang Sung ,  Jin-Sung Youn ,  Chang-Kyo Lee ,  Ju-Ho Jeon ,  Jin-Seok Heo

IPC: G06F12/00 ,  G06F3/06 ,  H04L25/03 ,  G11C29/02 ,  G11C5/04 ,  G11C29/12 ,  G11C11/407 ,  H01L25/18 ,  G11C29/44

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

公开(公告)号：US10600458B2

公开(公告)日：2020-03-24

申请号：US16105368

申请日：2018-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Ho Jeon ,  Han-Gi Jung ,  Hun-Dae Choi

IPC: G11C7/00 ,  G11C7/22 ,  H03L7/081 ,  H03L7/08 ,  G11C29/50 ,  H03K21/02 ,  G11C29/02

Abstract: A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

公开(公告)号：US11249662B2

公开(公告)日：2022-02-15

申请号：US16914724

申请日：2020-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wang-Soo Kim ,  Jung-Hwan Choi ,  Ki-Duk Park ,  Yoo-Chang Sung ,  Jin-Sung Youn ,  Chang-Kyo Lee ,  Ju-Ho Jeon ,  Jin-Seok Heo

IPC: G06F12/00 ,  G06F3/06 ,  H04L25/03 ,  G11C29/02 ,  G11C5/04 ,  G11C29/12 ,  G11C11/407 ,  H01L25/18 ,  G11C29/44

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

公开(公告)号：US11095121B2

公开(公告)日：2021-08-17

申请号：US16432962

申请日：2019-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Ho Jeon ,  Jin-Hee Park ,  Hyuck-Joon Kwon

IPC: H02H9/04 ,  H03K3/3565 ,  H02H1/00

Abstract: An electrostatic protection circuit with variable Schmitt trigger characteristics is provided. The electrostatic protection circuit uses a Schmitt trigger circuit to protect an integrated circuit against an overvoltage. The Schmitt trigger circuit includes first and second branches bridged between a power supply rail and a ground rail. The Schmitt trigger circuit operates with a narrow hysteresis width when the second branch is connected in parallel to the first branch and with a wide hysteresis width when the second branch is not connected in parallel to the first branch. The electrostatic protection circuit discharges an overvoltage of the power supply rail using a narrow hysteresis width when a weak overvoltage is applied to the power supply rail, and discharges an overvoltage of the power supply rail using a wide hysteresis width when a strong overvoltage is applied to the power supply rail.

公开(公告)号：US20190179553A1

公开(公告)日：2019-06-13

申请号：US16103078

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wang-Soo Kim ,  Jung-Hwan Choi ,  Ki-Duk Park ,  Yoo-Chang Sung ,  Jin-Sung Youn ,  Chang-Kyo Lee ,  Ju-Ho Jeon ,  Jin-Seok Heo

IPC: G06F3/06 ,  H04L25/03

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.