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公开(公告)号:US20180277474A1
公开(公告)日:2018-09-27
申请号:US15994004
申请日:2018-05-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: MuSeob SHIN , Won-young KIM , Sanghyun PARK , Jinchan AHN
IPC: H01L23/498 , H01L23/48 , H01L23/00 , H01L25/065 , H01L23/31
CPC classification number: H01L23/49838 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0655 , H01L25/0657 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81192 , H01L2224/81815 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15311 , H01L2924/3511 , H01L2924/014 , H01L2924/00014
Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.
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公开(公告)号:US20250029914A1
公开(公告)日:2025-01-23
申请号:US18430241
申请日:2024-02-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyunsoo CHUNG , Kwang-Soo KIM , Jinchan AHN
IPC: H01L23/498 , H01L23/00 , H01L25/065 , H10B80/00
Abstract: A semiconductor package includes a logic die that includes a backside power delivery network layer, an interposer die disposed on the logic die, a plurality of memory dies stacked on the interposer die, and a mold layer that covers the interposer die and the memory dies. Each of the logic die and the interposer die has a first width.
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