公开(公告)号：US20250115785A1

公开(公告)日：2025-04-10

申请号：US18771727

申请日：2024-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonki HUR ,  Seokjoo KIM ,  Daehoon YANG ,  Sanghyun PARK ,  Gayoung KIM ,  Sangkyun KIM ,  Inkwon KIM ,  Eunho SONG ,  Jaekwang CHOI

IPC: C09G1/02 ,  B24B37/04 ,  C09K3/14 ,  C09K15/30 ,  H01L21/321

Abstract: A slurry composition for chemical mechanical metal polishing includes a corrosion inhibitor, abrasive particles, an oxidizing agent, and a solvent. The corrosion inhibitor includes a C2 to C30 aliphatic heterocyclic compound including at least one nitrogen atom in the ring and at least one functional group selected from a halogen, an amine group, a cyclic amine group, a nitro group, an amide group, a carboxyl group, a hydroxy group, a thiol group, an alkoxy group, a C10 to C30 alkyl group, or an ester group; or a C2 to C30 aromatic heterocyclic compound including at least one nitrogen atom in the ring and at least one functional group selected from a halogen, an amine group, a cyclic amine group, a nitro group, an amide group, a carboxyl group, a hydroxy group, a thiol group, an alkoxy group, a C10 to C30 alkyl group, and an ester group; or a combination thereof.

公开(公告)号：US20250062228A1

公开(公告)日：2025-02-20

申请号：US18657084

申请日：2024-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun PARK ,  Gyuhee PARK ,  Inji LEE ,  Hase NAOKI

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

Abstract: A semiconductor device may include a substrate including devices; a lower insulating layer on the substrate; a lower wiring layer on the lower insulating layer and electrically connected to the devices; a first upper insulating layer on the lower insulating layer; an upper contact penetrating through the first upper insulating layer and connected to the lower wiring layer, an upper wiring layer on the first upper insulating layer and connected to the upper contact; and a second upper insulating layer on the first upper insulating layer and covering the upper wiring layer. The upper wiring layer may include an aluminum alloy and 0.01-3 wt % of the aluminum alloy may be at least one dopant among Zn, Ni, V, and Cr. A balance of the aluminum alloy may include Al.

公开(公告)号：US20180277474A1

公开(公告)日：2018-09-27

申请号：US15994004

申请日：2018-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： MuSeob SHIN ,  Won-young KIM ,  Sanghyun PARK ,  Jinchan AHN

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

公开(公告)号：US20240266291A1

公开(公告)日：2024-08-08

申请号：US18479211

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyoung LEE ,  Wei GUO ,  Wulin HE ,  Buseo CHOI ,  Sanghyun PARK ,  Wonwoong CHUNG

IPC: H01L23/532 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53219 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/5329

Abstract: A material including an alloy including aluminum of 99% by weight to 99.8% by weight, copper of 0.1% by weight to 0.5% by weight, and scandium of 0.1% by weight to 0.5% by weight, a metal line in a semiconductor device including the material, and a method for forming the metal line in the semiconductor device may be provided.

公开(公告)号：US20220122309A1

公开(公告)日：2022-04-21

申请号：US17426538

申请日：2020-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yejin KIM ,  Yoonjeong KANG ,  Iseul YU ,  Heeyul KIM ,  Sanghyun PARK ,  Jongil JEONG

IPC: G06T13/40 ,  G06T15/20 ,  G06T19/20 ,  G06T19/00 ,  G06V40/10 ,  G06V40/16 ,  G06T7/70

Abstract: An electronic device includes a camera, a display, and a processor, wherein the processor is configured to acquire an image using the camera, determine a 3D graphic object corresponding to an object included in the acquired image, and apply the determined 3D graphic object to a 3D avatar and display the same.

公开(公告)号：US20170207130A1

公开(公告)日：2017-07-20

申请号：US15386843

申请日：2016-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jung PARK ,  Ju-Hyun KIM ,  Hoyoung KIM ,  Boun YOON ,  TaeYong KWON ,  Sangkyun KIM ,  Sanghyun PARK

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/092 ,  H01L21/3105

CPC classification number: H01L21/823807 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/092

Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.

公开(公告)号：US20250024684A1

公开(公告)日：2025-01-16

申请号：US18672512

申请日：2024-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghyun PARK ,  Hyuncheol KIM ,  Suhwan LIM ,  Siyeon CHO

IPC: H10B51/20 ,  H10B51/30

Abstract: A vertical semiconductor device includes a substrate, a stacked structure including a plurality of insulation patterns and a plurality of gate electrode structures alternately and repeatedly stacked on the substrate in a vertical direction substantially perpendicular to a surface of the substrate, a channel pattern passing through the stacked structure, a gate insulation layer surrounding an outer wall of the channel pattern, and a gate insulation pattern disposed between the gate insulation layer and the gate electrode structures. The gate insulation layer includes a metal oxide having paraelectricity, and the gate insulation pattern has ferroelectricity. The gate insulation layer includes a first portion contacting one of the insulation patterns and a second portion contacting the gate insulation pattern.

公开(公告)号：US20240054694A1

公开(公告)日：2024-02-15

申请号：US18383963

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjun LEE ,  Minseoung WOO ,  Kyunghwa KIM ,  Sunho KIM ,  Sanghyun PARK

IPC: G06T11/00 ,  G06T3/40

CPC classification number: G06T11/00 ,  G06T3/40

Abstract: An electronic device according to various embodiments may include a display, a sensor configured to detect a distance from an actual item in a space, a camera configured to capture an image of a foreground, a memory configured to store a plurality of instructions, and a processor, wherein the plurality of instructions, when executed by the processor, cause the electronic device to analyze a first space using the camera and the sensor, store information of the first space and information related to a configuration of an object placed by a user in the first space, analyze a second space using the camera and the sensor, relocate the configuration of the object, based on information of the analyzed second space, and display the object having been relocated. Various other embodiments are possible.

公开(公告)号：US20230041033A1

公开(公告)日：2023-02-09

申请号：US17751146

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun PARK ,  Heangsu KIM ,  Jieun JUNG ,  Myungkeun OH ,  Jinwan AN

IPC: H04W8/20 ,  H04W8/18 ,  H04W12/30 ,  H04W12/06 ,  H04L9/32

Abstract: An electronic device includes a communication module, an embedded-subscriber identification module (eSIM) in which at least one profile is stored, and a processor. The processor is configured to, when accessing a server and succeeding in authentication for a first profile among at least one profile stored in the eSIM, receive an authentication token indicating successful authentication for the first profile from the server, when establishing communication with a first electronic device through the communication module, inform the first electronic device that the first profile is transmittable data, and when transmission of the first profile is requested from the first electronic device, transmit, to the first electronic device, the authentication token for downloading a second profile corresponding to the first profile from the server.

公开(公告)号：US20250151280A1

公开(公告)日：2025-05-08

申请号：US18918694

申请日：2024-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suseong NOH ,  Kwangsoo KIM ,  Taeyoung KIM ,  Ilho MYEONG ,  Sanghyun PARK ,  Suhwan LIM

IPC: H10B43/40 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device including a peripheral circuit structure, a cell structure including gate electrodes and stacked on the peripheral circuit structure, the cell structure including a cell region, a connection region, and a peripheral circuit connection region, the cell structure, a plurality of channel structures extending in a vertical direction through the gate electrodes in the cell region, each of the plurality of channel structures including a first end portion close to the peripheral circuit structure and a second end portion opposite to the first end portion, and a common source layer connected to the second end portion of each of the channel structures in the cell region may be provided.