公开(公告)号：US11411010B2

公开(公告)日：2022-08-09

申请号：US16865574

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Jisuk Park ,  Sungho Choi

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a first horizontal direction, each including a bit line; a plurality of buried contacts filling lower portions of spaces among the plurality of bit line structures on the substrate; a plurality of landing pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and being at the same level as the plurality of landing pads.

公开(公告)号：US12200924B2

公开(公告)日：2025-01-14

申请号：US17720945

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Jisuk Park ,  Sungho Choi

IPC: H10B12/00

Abstract: A semiconductor memory device includes a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a first horizontal direction, each including a bit line; a plurality of buried contacts filling lower portions of spaces among the plurality of bit line structures on the substrate; a plurality of landing pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and being at the same level as the plurality of landing pads.

公开(公告)号：US12048146B2

公开(公告)日：2024-07-23

申请号：US17680913

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Jisuk Park ,  Sungho Choi

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485

Abstract: A semiconductor memory device includes a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a first horizontal direction, each including a bit line; a plurality of buried contacts filling lower portions of spaces among the plurality of bit line structures on the substrate; a plurality of landing pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and being at the same level as the plurality of landing pads.

公开(公告)号：US11776583B2

公开(公告)日：2023-10-03

申请号：US16876023

申请日：2020-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Jisuk Park ,  Sungho Choi

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/528 ,  H10B12/00

CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L23/528 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor memory device includes a plurality of bit line structures including bit lines extending in parallel in a first lateral direction on a substrate, and a plurality of buried contacts and a plurality of landing pads. The plurality of buried contacts fill lower portions of spaces between the plurality of bit line structures on the substrate, and the plurality of landing pads fill upper portions of the spaces between the plurality of bit line structures and extend on the plurality of bit line structures. The plurality of landing pads have a hexagonal array structure, and central points of respective top surfaces of a first landing pad, a second landing pad, and a third landing pad, which are adjacent to each other from among the plurality of landing pads, are connected by a scalene triangle.

公开(公告)号：US20210118473A1

公开(公告)日：2021-04-22

申请号：US16876023

申请日：2020-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Jisuk Park ,  Sungho Choi

IPC: G11C5/06 ,  G11C5/02

Abstract: A semiconductor memory device includes a plurality of bit line structures including bit lines extending in parallel in a first lateral direction on a substrate, and a plurality of buried contacts and a plurality of landing pads. The plurality of buried contacts fill lower portions of spaces between the plurality of bit line structures on the substrate, and the plurality of landing pads fill upper portions of the spaces between the plurality of bit line structures and extend on the plurality of bit line structures. The plurality of landing pads have a hexagonal array structure, and central points of respective top surfaces of a first landing pad, a second landing pad, and a third landing pad, which are adjacent to each other from among the plurality of landing pads, are connected by a scalene triangle.