公开(公告)号：US11710715B2

公开(公告)日：2023-07-25

申请号：US17208005

申请日：2021-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Hyung Lee ,  Ki Tae Park ,  Byung Lyul Park ,  Joon Seok Oh ,  Jong Ho Yun

IPC: H01L25/10 ,  H01L23/00 ,  H01L25/18 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/24 ,  H01L24/05 ,  H01L24/25 ,  H01L25/105 ,  H01L25/18 ,  H01L23/3107 ,  H01L23/49822 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/2405 ,  H01L2224/2413 ,  H01L2224/24155 ,  H01L2224/2505 ,  H01L2224/25171 ,  H01L2224/25174 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.