公开(公告)号：US12199060B2

公开(公告)日：2025-01-14

申请号：US18143983

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbo Lee ,  Kwanhoo Son ,  Joon Seok Oh

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

公开(公告)号：US20240047357A1

公开(公告)日：2024-02-08

申请号：US18307109

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Jeon ,  Youngmin Kim ,  Joon Seok Oh ,  Changbo Lee

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L23/528 ,  H01L21/76843 ,  H01L21/76802 ,  H01L21/76877

Abstract: An interconnection structure includes a first dielectric layer, a second dielectric layer, first wiring patterns, and a first conductive pattern. The first wiring patterns respectively include a first penetration part that extends into a surface of the first dielectric layer, a first intervention part on the first penetration part and in the second dielectric layer, and a first connection part on the first intervention part and in the second dielectric layer. A top surface of the first intervention part is at a same level as a top surface of the first conductive pattern relative to the surface of the first dielectric layer. An angle between a sidewall of the first connection part and the top surface of the first intervention part is greater than that between a sidewall of the first penetration part and a bottom surface of the first dielectric layer.

公开(公告)号：US11710715B2

公开(公告)日：2023-07-25

申请号：US17208005

申请日：2021-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Hyung Lee ,  Ki Tae Park ,  Byung Lyul Park ,  Joon Seok Oh ,  Jong Ho Yun

IPC: H01L25/10 ,  H01L23/00 ,  H01L25/18 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/24 ,  H01L24/05 ,  H01L24/25 ,  H01L25/105 ,  H01L25/18 ,  H01L23/3107 ,  H01L23/49822 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/2405 ,  H01L2224/2413 ,  H01L2224/24155 ,  H01L2224/2505 ,  H01L2224/25171 ,  H01L2224/25174 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.

公开(公告)号：US11682648B2

公开(公告)日：2023-06-20

申请号：US17070540

申请日：2020-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbo Lee ,  Kwanhoo Son ,  Joon Seok Oh

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/528

CPC classification number: H01L24/20 ,  H01L21/566 ,  H01L21/6835 ,  H01L21/76871 ,  H01L23/315 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2224/214

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

公开(公告)号：US10559540B2

公开(公告)日：2020-02-11

申请号：US16004007

申请日：2018-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Bo Lee ,  Joon Seok Oh ,  Hyun Chul Jung ,  Jeong Ho Yeo

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: A fan-out semiconductor package includes a first connection member having a through-hole first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating the first and second semiconductor chips, a second connection member disposed on at least one side of the first and second semiconductor chips and including a redistribution layer electrically connected to the first and second semiconductor chips, and an insulating via in which at least a portion of the first connection member is removed in a thickness direction and is filled with an insulating material.