公开(公告)号：US20130187685A1

公开(公告)日：2013-07-25

申请号：US13737337

申请日：2013-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Phil Hong ,  Jenlung Liu ,  Nan Xing ,  Jae Jin Park

IPC: H03B19/00

CPC classification number: H03B19/00 ,  H03L7/00 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/50

Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.

Abstract translation: 抖动控制电路包括：伪随机数发生器，其响应于分频时钟信号产生伪随机数序列;以及抖动电路，其通过使用伪随机数的至少一个输出位来抖动输入数字代码 序列并输出对应于抖动结果的抖动数字码。 抖动电路可以作为抖动数字码，输出对应于输入数字码和输入数字码之和的数字代码，基于至少一个输出位。 抖动数字码可以被输入到与分频时钟信号同步操作的累加器。

公开(公告)号：US08847653B2

公开(公告)日：2014-09-30

申请号：US13737337

申请日：2013-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Phil Hong ,  Jenlung Liu ,  Nan Xing ,  Jae Jin Park

IPC: G06F1/04 ,  H03L7/00 ,  H03B19/00

CPC classification number: H03B19/00 ,  H03L7/00 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/50

Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.

Abstract translation: 抖动控制电路包括：伪随机数发生器，其响应于分频时钟信号产生伪随机数序列;以及抖动电路，其通过使用伪随机数的至少一个输出位来抖动输入数字代码 序列并输出对应于抖动结果的抖动数字码。 抖动电路可以作为抖动数字码，输出对应于输入数字码和输入数字码之和的数字代码，基于至少一个输出位。 抖动数字码可以被输入到与分频时钟信号同步操作的累加器。