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Patent Agency Ranking
公开(公告)号：US08847653B2
公开(公告)日：2014-09-30
申请号：US13737337
申请日：2013-01-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong Phil Hong , Jenlung Liu , Nan Xing , Jae Jin Park
CPC classification number: H03B19/00 , H03L7/00 , H03L7/099 , H03L7/16 , H03L2207/50
Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.
Abstract translation: 抖动控制电路包括：伪随机数发生器，其响应于分频时钟信号产生伪随机数序列;以及抖动电路，其通过使用伪随机数的至少一个输出位来抖动输入数字代码 序列并输出对应于抖动结果的抖动数字码。 抖动电路可以作为抖动数字码，输出对应于输入数字码和输入数字码之和的数字代码，基于至少一个输出位。 抖动数字码可以被输入到与分频时钟信号同步操作的累加器。
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公开(公告)号：US09214946B2
公开(公告)日：2015-12-15
申请号：US14108834
申请日：2013-12-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nan Xing , Jaejin Park , Jenlung Liu , Tae-Kwang Jang
CPC classification number: H03L7/093 , H03L7/0895
Abstract: A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal.
Abstract translation: 提供了一种锁相环电路，其包括一个轰击相位频率检测器，配置为接收参考信号和反馈信号，检测参考信号和反馈信号之间的相位差，基于结果输出检测信号 的检测; 模拟数字混合滤波器，被配置为接收检测信号并根据接收到的检测信号输出控制信号; 被配置为响应于所述控制信号输出输出信号的压控振荡器; 以及分频器，被配置为将输出信号除以n作为反馈信号输出。 检测信号是数字信号，控制信号是模拟信号。
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公开(公告)号：US20130187685A1
公开(公告)日：2013-07-25
申请号：US13737337
申请日：2013-01-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong Phil Hong , Jenlung Liu , Nan Xing , Jae Jin Park
IPC: H03B19/00
CPC classification number: H03B19/00 , H03L7/00 , H03L7/099 , H03L7/16 , H03L2207/50
Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.
Abstract translation: 抖动控制电路包括：伪随机数发生器，其响应于分频时钟信号产生伪随机数序列;以及抖动电路，其通过使用伪随机数的至少一个输出位来抖动输入数字代码 序列并输出对应于抖动结果的抖动数字码。 抖动电路可以作为抖动数字码，输出对应于输入数字码和输入数字码之和的数字代码，基于至少一个输出位。 抖动数字码可以被输入到与分频时钟信号同步操作的累加器。
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4.发明授权公开(公告)号：US09618958B2
公开(公告)日：2017-04-11
申请号：US14203797
申请日：2014-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae Kwang Jang , Jen Lung Liu , Nan Xing , Jae Jin Park
Abstract: A current generator includes a first current generation circuit configured to generate a first current having a first current noise which depends on a change in a supply voltage, a second current generation circuit configured to generate a second current having a second current noise which depends on the change in the supply voltage, and a current subtracting circuit configured to generate a third current with the first current noise and the second current noise removed by subtracting the second current from the first current.
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公开(公告)号：US08981828B2
公开(公告)日：2015-03-17
申请号：US14199139
申请日：2014-03-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae Kwang Jang , Jen Lung Liu , Nan Xing , Jae Jin Park
CPC classification number: H03K5/15 , H03K5/1504 , H03K5/1508
Abstract: A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units.
Abstract translation: 多相发生器包括：振荡器单元，包括形成单个闭环的多个第一缓冲单元和包括分别连接到多个节点的多个第二缓冲单元的延迟单元，其中多个节点中的每一个连接在 第一缓冲单元的两个相邻缓冲单元。 在第一缓冲单元中，第二缓冲单元中的第二缓冲单元的输出信号的相位滞后于第一缓冲单元的输出信号的相位。
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