公开(公告)号：US08981824B2

公开(公告)日：2015-03-17

申请号：US14201285

申请日：2014-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jin Park ,  Tae Kwang Jang ,  Jenlung Liu

IPC: H03L7/06 ,  H03L7/10

CPC classification number: H03L7/10 ,  H03L7/095 ,  H03L7/0997 ,  H03L2207/50

Abstract: A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.

Abstract translation: 操作诸如全数字PLL的锁相环（PLL）的方法包括将参考时钟信号与PLL的反馈信号进行比较并根据比较结果输出比较信号的操作，以及检测是否 PLL通过使用比较信号切换的次数处于锁定状态。

公开(公告)号：US08847653B2

公开(公告)日：2014-09-30

申请号：US13737337

申请日：2013-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Phil Hong ,  Jenlung Liu ,  Nan Xing ,  Jae Jin Park

IPC: G06F1/04 ,  H03L7/00 ,  H03B19/00

CPC classification number: H03B19/00 ,  H03L7/00 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/50

Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.

Abstract translation: 抖动控制电路包括：伪随机数发生器，其响应于分频时钟信号产生伪随机数序列;以及抖动电路，其通过使用伪随机数的至少一个输出位来抖动输入数字代码 序列并输出对应于抖动结果的抖动数字码。 抖动电路可以作为抖动数字码，输出对应于输入数字码和输入数字码之和的数字代码，基于至少一个输出位。 抖动数字码可以被输入到与分频时钟信号同步操作的累加器。

公开(公告)号：US09214946B2

公开(公告)日：2015-12-15

申请号：US14108834

申请日：2013-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nan Xing ,  Jaejin Park ,  Jenlung Liu ,  Tae-Kwang Jang

IPC: H03L7/06 ,  H03L7/093 ,  H03L7/089

CPC classification number: H03L7/093 ,  H03L7/0895

Abstract: A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal.

Abstract translation: 提供了一种锁相环电路，其包括一个轰击相位频率检测器，配置为接收参考信号和反馈信号，检测参考信号和反馈信号之间的相位差，基于结果输出检测信号 的检测; 模拟数字混合滤波器，被配置为接收检测信号并根据接收到的检测信号输出控制信号; 被配置为响应于所述控制信号输出输出信号的压控振荡器; 以及分频器，被配置为将输出信号除以n作为反馈信号输出。 检测信号是数字信号，控制信号是模拟信号。

公开(公告)号：US20130187685A1

公开(公告)日：2013-07-25

申请号：US13737337

申请日：2013-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Phil Hong ,  Jenlung Liu ,  Nan Xing ,  Jae Jin Park

IPC: H03B19/00

CPC classification number: H03B19/00 ,  H03L7/00 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/50

Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.

Abstract translation: 抖动控制电路包括：伪随机数发生器，其响应于分频时钟信号产生伪随机数序列;以及抖动电路，其通过使用伪随机数的至少一个输出位来抖动输入数字代码 序列并输出对应于抖动结果的抖动数字码。 抖动电路可以作为抖动数字码，输出对应于输入数字码和输入数字码之和的数字代码，基于至少一个输出位。 抖动数字码可以被输入到与分频时钟信号同步操作的累加器。