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公开(公告)号：US08847653B2
公开(公告)日：2014-09-30
申请号：US13737337
申请日：2013-01-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong Phil Hong , Jenlung Liu , Nan Xing , Jae Jin Park
CPC classification number: H03B19/00 , H03L7/00 , H03L7/099 , H03L7/16 , H03L2207/50
Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.
Abstract translation: 抖动控制电路包括：伪随机数发生器，其响应于分频时钟信号产生伪随机数序列;以及抖动电路，其通过使用伪随机数的至少一个输出位来抖动输入数字代码 序列并输出对应于抖动结果的抖动数字码。 抖动电路可以作为抖动数字码，输出对应于输入数字码和输入数字码之和的数字代码，基于至少一个输出位。 抖动数字码可以被输入到与分频时钟信号同步操作的累加器。
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公开(公告)号：US09933799B2
公开(公告)日：2018-04-03
申请号：US15271680
申请日：2016-09-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun Hyeok Yang , Dae Yong Kim , Sang Ho Kim , Jae Jin Park
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: A voltage regulator includes an error amplifier configured to receive a first voltage through a first node as an operating voltage, to amplify a difference between a reference voltage and a feedback voltage, and to output an amplified voltage; a power transistor connected between a second node through which a second voltage is supplied and an output node of the voltage regulator; and a switch circuit configured to select a level of a gate voltage supplied to a gate of the power transistor and level of a body voltage supplied to a body of the power transistor in response to a first power sequence of the first voltage, a second power sequence of the second voltage, and an operation control signal.
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3.发明授权公开(公告)号：US08981824B2
公开(公告)日：2015-03-17
申请号：US14201285
申请日：2014-03-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Jin Park , Tae Kwang Jang , Jenlung Liu
CPC classification number: H03L7/10 , H03L7/095 , H03L7/0997 , H03L2207/50
Abstract: A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.
Abstract translation: 操作诸如全数字PLL的锁相环（PLL）的方法包括将参考时钟信号与PLL的反馈信号进行比较并根据比较结果输出比较信号的操作，以及检测是否 PLL通过使用比较信号切换的次数处于锁定状态。
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公开(公告)号：US10146985B2
公开(公告)日：2018-12-04
申请号：US15438463
申请日：2017-02-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae Young Chung , Jae Jin Park , Hee Chang Hwang
IPC: G06K9/00
Abstract: A sensing read-out circuit includes an amplifier circuit that converts a charge output from a sensing line of a sensor into a first voltage, another amplifier circuit that converts a charge output from another sensing line into a second voltage, another amplifier circuit that generates a first amplified voltage by amplifying a difference between the first voltage and the second voltage, an analog-to-digital converter that converts the first amplified voltage into a digital signal, a first mixer that generates a second mixed signal by mixing the first digital signal and an in-phase clock signal, a second mixer that generates a second mixed signal by mixing the first digital signal and a quadrature-phase clock signal, a first filter that generates an in-phase signal by performing low-pass filtering on the first mixed signal, and a second filter that generates a quadrature-phase signal by performing low-pass filtering on the second mixed signal.
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Patent Agency Ranking
公开(公告)号：US20180039809A1
公开(公告)日：2018-02-08
申请号：US15438463
申请日：2017-02-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： DAE YOUNG CHUNG , Jae Jin Park , Hee Chang Hwang
CPC classification number: G06K9/0002 , G06K9/00013 , G06K9/00046
Abstract: A sensing read-out circuit includes an amplifier circuit that converts a charge output from a sensing line of a sensor into a first voltage, another amplifier circuit that converts a charge output from another sensing line into a second voltage, another amplifier circuit that generates a first amplified voltage by amplifying a difference between the first voltage and the second voltage, an analog-to-digital converter that converts the first amplified voltage into a digital signal, a first mixer that generates a second mixed signal by mixing the first digital signal and an in-phase clock signal, a second mixer that generates a second mixed signal by mixing the first digital signal and a quadrature-phase clock signal, a first filter that generates an in-phase signal by performing low-pass filtering on the first mixed signal, and a second filter that generates a quadrature-phase signal by performing low-pass filtering on the second mixed signal.
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公开(公告)号：US20130187685A1
公开(公告)日：2013-07-25
申请号：US13737337
申请日：2013-01-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong Phil Hong , Jenlung Liu , Nan Xing , Jae Jin Park
IPC: H03B19/00
CPC classification number: H03B19/00 , H03L7/00 , H03L7/099 , H03L7/16 , H03L2207/50
Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.
Abstract translation: 抖动控制电路包括：伪随机数发生器，其响应于分频时钟信号产生伪随机数序列;以及抖动电路，其通过使用伪随机数的至少一个输出位来抖动输入数字代码 序列并输出对应于抖动结果的抖动数字码。 抖动电路可以作为抖动数字码，输出对应于输入数字码和输入数字码之和的数字代码，基于至少一个输出位。 抖动数字码可以被输入到与分频时钟信号同步操作的累加器。
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公开(公告)号：US10726228B2
公开(公告)日：2020-07-28
申请号：US15648320
申请日：2017-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hee Chang Hwang , Jae Jin Park , Min Chul Lee , Seung Hoon Lee , Dae Young Chung
IPC: G06K9/00 , H01L23/528
Abstract: A semiconductor device comprising a fingerprint sensor configured to generate first-direction sensing data and second-direction sensing data by sensing a fingerprint image in a first direction and a second direction, respectively, which is perpendicular to the first direction; a differential sensing circuit configured to generate first-direction first differential data and second-direction first differential data by performing a differential operation on the first-direction sensing data and the second-direction sensing data, respectively; and a fingerprint processing circuit configured to generate first-direction second differential data and second-direction second differential data by performing a differential operation on the first-direction first differential data and the second-direction first differential data, respectively, and generate fingerprint data by adding the first-direction second differential data and the second-direction second differential data.
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8.发明授权公开(公告)号：US09618958B2
公开(公告)日：2017-04-11
申请号：US14203797
申请日：2014-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae Kwang Jang , Jen Lung Liu , Nan Xing , Jae Jin Park
Abstract: A current generator includes a first current generation circuit configured to generate a first current having a first current noise which depends on a change in a supply voltage, a second current generation circuit configured to generate a second current having a second current noise which depends on the change in the supply voltage, and a current subtracting circuit configured to generate a third current with the first current noise and the second current noise removed by subtracting the second current from the first current.
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公开(公告)号：US08981828B2
公开(公告)日：2015-03-17
申请号：US14199139
申请日：2014-03-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae Kwang Jang , Jen Lung Liu , Nan Xing , Jae Jin Park
CPC classification number: H03K5/15 , H03K5/1504 , H03K5/1508
Abstract: A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units.
Abstract translation: 多相发生器包括：振荡器单元，包括形成单个闭环的多个第一缓冲单元和包括分别连接到多个节点的多个第二缓冲单元的延迟单元，其中多个节点中的每一个连接在 第一缓冲单元的两个相邻缓冲单元。 在第一缓冲单元中，第二缓冲单元中的第二缓冲单元的输出信号的相位滞后于第一缓冲单元的输出信号的相位。
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