Abstract:
A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.
Abstract:
A voltage regulator includes an error amplifier configured to receive a first voltage through a first node as an operating voltage, to amplify a difference between a reference voltage and a feedback voltage, and to output an amplified voltage; a power transistor connected between a second node through which a second voltage is supplied and an output node of the voltage regulator; and a switch circuit configured to select a level of a gate voltage supplied to a gate of the power transistor and level of a body voltage supplied to a body of the power transistor in response to a first power sequence of the first voltage, a second power sequence of the second voltage, and an operation control signal.
Abstract:
A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.
Abstract:
A sensing read-out circuit includes an amplifier circuit that converts a charge output from a sensing line of a sensor into a first voltage, another amplifier circuit that converts a charge output from another sensing line into a second voltage, another amplifier circuit that generates a first amplified voltage by amplifying a difference between the first voltage and the second voltage, an analog-to-digital converter that converts the first amplified voltage into a digital signal, a first mixer that generates a second mixed signal by mixing the first digital signal and an in-phase clock signal, a second mixer that generates a second mixed signal by mixing the first digital signal and a quadrature-phase clock signal, a first filter that generates an in-phase signal by performing low-pass filtering on the first mixed signal, and a second filter that generates a quadrature-phase signal by performing low-pass filtering on the second mixed signal.
Abstract:
A sensing read-out circuit includes an amplifier circuit that converts a charge output from a sensing line of a sensor into a first voltage, another amplifier circuit that converts a charge output from another sensing line into a second voltage, another amplifier circuit that generates a first amplified voltage by amplifying a difference between the first voltage and the second voltage, an analog-to-digital converter that converts the first amplified voltage into a digital signal, a first mixer that generates a second mixed signal by mixing the first digital signal and an in-phase clock signal, a second mixer that generates a second mixed signal by mixing the first digital signal and a quadrature-phase clock signal, a first filter that generates an in-phase signal by performing low-pass filtering on the first mixed signal, and a second filter that generates a quadrature-phase signal by performing low-pass filtering on the second mixed signal.
Abstract:
A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.
Abstract:
A semiconductor device comprising a fingerprint sensor configured to generate first-direction sensing data and second-direction sensing data by sensing a fingerprint image in a first direction and a second direction, respectively, which is perpendicular to the first direction; a differential sensing circuit configured to generate first-direction first differential data and second-direction first differential data by performing a differential operation on the first-direction sensing data and the second-direction sensing data, respectively; and a fingerprint processing circuit configured to generate first-direction second differential data and second-direction second differential data by performing a differential operation on the first-direction first differential data and the second-direction first differential data, respectively, and generate fingerprint data by adding the first-direction second differential data and the second-direction second differential data.
Abstract:
A current generator includes a first current generation circuit configured to generate a first current having a first current noise which depends on a change in a supply voltage, a second current generation circuit configured to generate a second current having a second current noise which depends on the change in the supply voltage, and a current subtracting circuit configured to generate a third current with the first current noise and the second current noise removed by subtracting the second current from the first current.
Abstract:
A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units.