公开(公告)号：US20160020324A1

公开(公告)日：2016-01-21

申请号：US14573429

申请日：2014-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pan-Kwi Park ,  Koung-Min Ryu ,  Moon-Han Park ,  Hyung-suk Jung ,  Jong-hoon Baek ,  Su-Young Choi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.

Abstract translation: 半导体器件包括应力源和绝缘图案。 形成器件隔离层以限定衬底上的有源区。 在有源区上形成第一栅电极。 在器件隔离层上形成第二栅电极。 在第一栅极电极和第二栅极电极之间的有源区域中形成沟槽。 在沟槽中形成应力源。 设置在应力器和器件隔离层之间并与第二栅电极相邻的空腔。 在空腔中形成绝缘图案。

公开(公告)号：US09793399B2

公开(公告)日：2017-10-17

申请号：US14573429

申请日：2014-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pan-Kwi Park ,  Koung-Min Ryu ,  Moon-Han Park ,  Hyung-suk Jung ,  Jong-hoon Baek ,  Su-Young Choi

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.