公开(公告)号：US20230217660A1

公开(公告)日：2023-07-06

申请号：US18062837

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungil LEE ,  Sehoon Lee

IPC: H01L29/76

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor device includes a lower structure, stack structure including gate electrodes stacked and spaced apart from each other on a first region of the lower structure and extending in a staircase shape on a second region of the lower structure, and interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating through the gate electrodes on the first region, and isolation structures penetrating through the gate electrodes spaced apart from each other. Each channel structure a channel bent portion between first and second channel structures. Each isolation structure includes a first isolation bent portion between first and second isolation structures and a second isolation bent portion between second and third isolation structures. A width of an upper surface of the second isolation structure is narrower than a width of a lower surface of the third isolation structure.

公开(公告)号：US20240222267A1

公开(公告)日：2024-07-04

申请号：US18396813

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungil LEE ,  Seungbeom KO ,  Jongyoon CHOI

IPC: H01L23/522 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5226 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device comprising: a stack structure on a substrate including gate electrodes and insulating layers alternately stacked; a first through via extending through the stack structure; and a second through via spaced apart from the first through via, wherein the second through via extends through the stack structure, wherein the second through via is electrically connected to a first gate electrode that is farthest one among the gate electrodes from the substrate in the vertical direction, wherein a gate pad is on and contacts the first gate electrode, and the first through via includes: a vertical pattern; first and second protrusions that protrude from the vertical pattern, wherein the first protrusion overlaps a portion of the first gate electrode in the horizontal direction; and the second protrusion overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is spaced apart from the second through via.

公开(公告)号：US20190325939A1

公开(公告)日：2019-10-24

申请号：US16502943

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JoongShik SHIN ,  Byoungil LEE ,  Hyunmog PARK ,  Euntaek JUNG

IPC: G11C11/408 ,  G11C11/06 ,  G11C8/12 ,  G11C8/08 ,  H01L27/11582 ,  H01L21/8239 ,  H01L27/11573 ,  H01L27/11565 ,  G11C8/14 ,  H01L23/528 ,  H01L27/11575

Abstract: A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.