公开(公告)号：US11515421B2

公开(公告)日：2022-11-29

申请号：US17205282

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Joohee Jung ,  Jaehyeoung Ma ,  Namhyun Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.

公开(公告)号：US20230139447A1

公开(公告)日：2023-05-04

申请号：US18148233

申请日：2022-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggun YOU ,  Sungil Park ,  Joohee Jung ,  Sunggi Hur

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.

公开(公告)号：US11171133B2

公开(公告)日：2021-11-09

申请号：US16927636

申请日：2020-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin Park ,  Dongil Bae ,  Daewon Kim ,  Taeyoung Kim ,  Joohee Jung ,  Jaehoon Shin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.

公开(公告)号：US11990549B2

公开(公告)日：2024-05-21

申请号：US17716005

申请日：2022-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jung ,  Jinbum Kim ,  Dongil Bae

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions.

公开(公告)号：US11699703B2

公开(公告)日：2023-07-11

申请号：US17451688

申请日：2021-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin Park ,  Dongil Bae ,  Daewon Kim ,  Taeyoung Kim ,  Joohee Jung ,  Jaehoon Shin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.

公开(公告)号：US12149376B2

公开(公告)日：2024-11-19

申请号：US17958967

申请日：2022-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonhye Baek ,  Gulji Chung ,  Para Kang ,  Changwon Kim ,  Joohee Park ,  Youngchan Woo ,  Joohee Jung

IPC: H04L12/28 ,  H04L41/08

Abstract: An electronic device may include: a communication module; a processor operatively connected to the communication module; and a memory operatively connected to the processor and configured to store computer program code. The computer program code, when executed, enables the processor to: upon detection of execution of a first operation of a first Internet of Things (IoT) device, obtain, from the memory, a first instruction to operate the first IoT device in a second operation; transmit the first instruction to the first IoT device to operate the first IoT device in the second operation; and monitor execution of the second operation by the first IoT device.

公开(公告)号：US11545489B2

公开(公告)日：2023-01-03

申请号：US17180989

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggun You ,  Sungil Park ,  Joohee Jung ,  Sunggi Hur

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.

公开(公告)号：US11302815B2

公开(公告)日：2022-04-12

申请号：US16866628

申请日：2020-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jung ,  Jinbum Kim ,  Dongil Bae

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L27/088

Abstract: A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions.

公开(公告)号：US12040401B2

公开(公告)日：2024-07-16

申请号：US17994565

申请日：2022-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Joohee Jung ,  Jaehyeoung Ma ,  Namhyun Lee

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/42392 ,  H01L2029/7858

Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.

公开(公告)号：US11996406B2

公开(公告)日：2024-05-28

申请号：US18148233

申请日：2022-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggun You ,  Sungil Park ,  Joohee Jung ,  Sunggi Hur

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823456 ,  H01L21/823481

Abstract: A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.