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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220157811A1

    公开(公告)日：2022-05-19

    申请号：US17380232

    申请日：2021-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggun YOU ,  Sung Gi HUR ,  Sungil PARK ,  Wooseok PARK ,  Seungmin SONG

    IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8238

    Abstract: A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region, the first active pattern including first source/drain patterns and a first channel pattern between the first source/drain patterns; a second active pattern on the second region, the second active pattern including second source/drain patterns and a second channel pattern between the second source/drain patterns; and a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, wherein a length of the first channel pattern is greater than a length of the second channel pattern, each of the first channel pattern and the second channel pattern includes a plurality of semiconductor patterns stacked on the substrate, and at least two semiconductor patterns of the first channel pattern are bent away from or toward a bottom surface of the substrate.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220181489A1

    公开(公告)日：2022-06-09

    申请号：US17380256

    申请日：2021-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggun YOU ,  Yoonjoong KIM ,  Seungwoo DO ,  Sungil PARK

    IPC: H01L29/78 ,  H01L29/10

    Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220037521A1

    公开(公告)日：2022-02-03

    申请号：US17205282

    申请日：2021-03-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggun YOU ,  Joohee JUNG ,  Jaehyeoung MA ,  Namhyun LEE

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06

    Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.

    SEMICONDUCTOR DEVICES
    6.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240128335A1

    公开(公告)日：2024-04-18

    申请号：US18369236

    申请日：2023-09-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggun YOU ,  Junki PARK ,  Sunghwan KIM ,  Wandon KIM ,  Sughyun SUNG ,  Hyunbae LEE

    IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device includes an active region on a substrate, a plurality of channel layers spaced apart from each other, a gate structure on the substrate, a source/drain region on at least one side of the gate structure, and a contact plug connected to the source/drain region. The contact plug includes a metal-semiconductor compound layer and a barrier layer on the metal-semiconductor compound layer. The contact plug includes a first inclined surface and a second inclined surface positioned where the metal-semiconductor compound layer and the barrier layer directly contact each other. The barrier layer includes first and second ends protruding towards the gate structure. The first and second ends are positioned at a level higher than an upper surface of an uppermost channel layer. An uppermost portion of the metal-semiconductor compound layer is positioned at a level higher than an upper surface of the source/drain region.

    SEMICONDUCTOR DEVICE
    7.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240088295A1

    公开(公告)日：2024-03-14

    申请号：US18518004

    申请日：2023-11-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junggun YOU ,  Yoonjoong KIM ,  Seungwoo DO ,  Sungil PARK

    IPC: H01L29/78 ,  H01L29/10

    CPC classification number: H01L29/7848 ,  H01L29/1033

    Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

    SEMICONDUCTOR DEVICES
    8.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220020742A1

    公开(公告)日：2022-01-20

    申请号：US17180989

    申请日：2021-02-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junggun YOU ,  Sungil PARK ,  Joohee JUNG ,  Sunggi HUR

    IPC: H01L27/088 ,  H01L21/8234

    Abstract: A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.

    SEMICONDUCTOR DEVICES HAVING ASYMMETRICAL STRUCTURES
    10.
    发明申请
    SEMICONDUCTOR DEVICES HAVING ASYMMETRICAL STRUCTURES 有权

    公开(公告)号：US20230139447A1

    公开(公告)日：2023-05-04

    申请号：US18148233

    申请日：2022-12-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junggun YOU ,  Sungil Park ,  Joohee Jung ,  Sunggi Hur

    IPC: H01L27/088 ,  H01L21/8234

    Abstract: A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.

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