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公开(公告)号:US20240422975A1
公开(公告)日:2024-12-19
申请号:US18590354
申请日:2024-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kwangyoung Jung , Sunil Shim , Seung-Jun Lee , Joohyun Lim , Yoojin Jeon
Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure on a peripheral substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a cell array region and an outer region, a source structure on the cell array region, a base pattern on the outer region, a cell vertical structure that extends into the cell array structure in the cell array region and is electrically connected to the source structure, an outer vertical structure that extends into the cell array structure in the outer region, and a filling pattern that extends from the outer vertical structure and into the base pattern. The filling pattern defines a void, a top end of the cell vertical structure extends from the peripheral substrate by a first distance, and a top surface of the source structure extends from the peripheral substrate by a second distance.
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公开(公告)号:US20240179914A1
公开(公告)日:2024-05-30
申请号:US18510209
申请日:2023-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chulmin Choi , Sunil Shim , Joohyun Lim
Abstract: A semiconductor device includes a gate electrode structure including first to fourth gate electrodes, a first memory channel structure extending through the first to third gate electrodes, a second memory channel structure contacting an upper surface of the first memory channel structure and extending through the fourth gate electrode, and a first contact plug including a lower portion extending partially through the gate electrode structure and an upper portion on and contacting an upper surface of the lower portion. The lower portion of the first contact plug has a varying width, and the upper portion of the first contact plug has a width gradually increasing from a bottom toward a top thereof. The lower portion of the first contact plug extends through the first, second and third gate electrodes, and is electrically insulated from the first and second gate electrodes, and is electrically connected to the third gate electrode.
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