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    Memory device and operation method thereof
    1.
    发明授权
    Memory device and operation method thereof 有权

    公开(公告)号：US12032838B2

    公开(公告)日：2024-07-09

    申请号：US17721450

    申请日：2022-04-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoojin Nam ,  Woongdai Kang ,  Seung-Jun Lee ,  Dongyeong Choi

    IPC: G06F3/06

    CPC classification number: G06F3/0632 ,  G06F3/0625 ,  G06F3/0679

    Abstract: Disclosed is an operation method of a memory device which performs a self-refresh operation. The method includes receiving a deep-sleep mode enter command from a memory controller, changing a magnitude of an internal voltage of the memory device from a first voltage to a second voltage smaller than the first voltage, in response to the deep-sleep mode enter command, and entering a self-refresh mode under control of the memory controller, and the internal voltage is maintained at the second voltage during the self-refresh mode.

    SEMICONDUCTOR MEMORY DEVICES HAVING ADJUSTABLE I/O SIGNAL LINE LOADING THAT SUPPORTS REDUCED POWER CONSUMPTION DURING READ AND WRITE OPERATIONS
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES HAVING ADJUSTABLE I/O SIGNAL LINE LOADING THAT SUPPORTS REDUCED POWER CONSUMPTION DURING READ AND WRITE OPERATIONS 审中-公开

    公开(公告)号：US20240105255A1

    公开(公告)日：2024-03-28

    申请号：US18322894

    申请日：2023-05-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Jun Lee ,  Sang-Yun Kim ,  Jonghyuk Kim ,  Bok-Yeon Won

    IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4093

    CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4093

    Abstract: A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n-1th connection control transistor is configured to electrically short the n-1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank. A control circuit is provided, which is configured to reduce I/O signal line power consumption within the memory device during read (and write) operations.

    MEMORY DEVICE AND OPERATION METHOD THEREOF
    5.
    发明公开
    MEMORY DEVICE AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20240329862A1

    公开(公告)日：2024-10-03

    申请号：US18739263

    申请日：2024-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YooJin Nam ,  Woongdai Kang ,  Seung-Jun Lee ,  Dongyeong Choi

    IPC: G06F3/06

    CPC classification number: G06F3/0632 ,  G06F3/0625 ,  G06F3/0679

    Abstract: Disclosed is an operation method of a memory device which performs a self-refresh operation. The method includes receiving a deep-sleep mode enter command from a memory controller, changing a magnitude of an internal voltage of the memory device from a first voltage to a second voltage smaller than the first voltage, in response to the deep-sleep mode enter command, and entering a self-refresh mode under control of the memory controller, and the internal voltage is maintained at the second voltage during the self-refresh mode.

    Semiconductor devices including capacitors and methods of manufacturing the same
    6.
    发明授权
    Semiconductor devices including capacitors and methods of manufacturing the same 有权
    包括电容器的半导体器件及其制造方法

    公开(公告)号：US09431476B2

    公开(公告)日：2016-08-30

    申请号：US15087349

    申请日：2016-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

    IPC: H01L21/00 ,  H01L49/02 ,  H01L27/108 ,  H01L21/764

    CPC classification number: H01L28/88 ,  H01L21/764 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/90

    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

    Abstract translation: 半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。 第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。 第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。 绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

    Semiconductor Devices Having a Supporter and Methods of Fabricating the Same
    7.
    发明申请
    Semiconductor Devices Having a Supporter and Methods of Fabricating the Same 有权
    具有支持者的半导体器件及其制造方法

    公开(公告)号：US20160049460A1

    公开(公告)日：2016-02-18

    申请号：US14636397

    申请日：2015-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Seung-Jun Lee ,  Young-Seung Cho

    IPC: H01L49/02

    CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/90

    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括在半导体衬底上的层间绝缘层，半导体衬底上的接触焊盘并穿透层间绝缘层，层间绝缘层上的停止绝缘层，接触焊盘上的存储电极，上部部分之间的上部支撑 存储电极，存储电极和上支撑体之间的侧支撑体，存储电极上的电容器电介质层，侧支撑体和上支撑件，以及电容器介电层上的平板电极。

    SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METHODS OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METHODS OF MANUFACTURING THE SAME 审中-公开
    包括电容器的半导体器件及其制造方法

    公开(公告)号：US20160225845A1

    公开(公告)日：2016-08-04

    申请号：US15087349

    申请日：2016-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

    IPC: H01L49/02

    CPC classification number: H01L28/88 ,  H01L21/764 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/90

    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

    Abstract translation: 半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。 第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。 第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。 绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    9.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20240422975A1

    公开(公告)日：2024-12-19

    申请号：US18590354

    申请日：2024-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwangyoung Jung ,  Sunil Shim ,  Seung-Jun Lee ,  Joohyun Lim ,  Yoojin Jeon

    IPC: H10B43/27 ,  H10B43/40

    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure on a peripheral substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a cell array region and an outer region, a source structure on the cell array region, a base pattern on the outer region, a cell vertical structure that extends into the cell array structure in the cell array region and is electrically connected to the source structure, an outer vertical structure that extends into the cell array structure in the outer region, and a filling pattern that extends from the outer vertical structure and into the base pattern. The filling pattern defines a void, a top end of the cell vertical structure extends from the peripheral substrate by a first distance, and a top surface of the source structure extends from the peripheral substrate by a second distance.

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