公开(公告)号：US09390812B2

公开(公告)日：2016-07-12

申请号：US14713458

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  In-Gyu Park ,  Jung-Hak Song

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  G11C29/02 ,  G11C29/50 ,  G11C29/12

CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/027 ,  G11C2029/1206 ,  G11C2029/5006

Abstract: An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two.

Abstract translation: 提供电子熔断器测试装置。 电熔丝测试装置可以包括第一晶体管和连接到第一晶体管的源极/漏极端子的熔丝阵列。 熔丝阵列可以包括n个熔丝组，每个熔丝组可以包括在一端和另一端之间彼此串联连接的一端，另一端和m个第一熔丝元件， 熔丝组可以彼此连接，并且每个熔丝组的另一端可以连接到第一晶体管的源极/漏极端子，并且n和m是等于或大于2的自然数。

公开(公告)号：US11942143B2

公开(公告)日：2024-03-26

申请号：US17559110

申请日：2021-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Jung-Hak Song

IPC: G11C11/4097 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096

Abstract: A semiconductor memory device includes a memory cell array that includes memory cells arranged in rows and columns, a row decoder that is configured to receive a row address, decode the row address, and adjust voltages of selection lines based on the decoded row address, a word line driver that is connected with the selection lines, is connected with the rows of the memory cells through word lines, and is configured to adjust voltages of the word lines in response to an internal clock signal and the voltages of the selection lines, and a detection circuit that is connected with the word lines and is configured to activate a detection signal in response to voltages of the word lines being identical at a specific timing.