公开(公告)号：US09235466B2

公开(公告)日：2016-01-12

申请号：US13915179

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Jong-Pil Son ,  Jung-bae Lee

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/37 ,  G11C29/04

CPC classification number: G06F11/1012 ,  G06F11/10 ,  G06F11/1024 ,  G06F11/1048 ,  G06F11/106 ,  G11C2029/0411 ,  H03M13/3707

Abstract: An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.

Abstract translation: 纠错装置包括：纠错电路，被配置为对存储器件的多个存储单元的至少一个写入和读出的数据的一部分进行选择性地执行纠错。 数据的部分是从多个存储器单元的子集写入和读出中的至少一个，并且该子集仅包括多个存储器单元中的故障单元。 误差校正装置还包括故障地址存储电路，其被配置为存储故障单元的地址信息。