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公开(公告)号：US10380029B2
公开(公告)日：2019-08-13
申请号：US15633889
申请日：2017-06-27
发明人： Jae-Don Lee , Min-Kyu Jeong , Jong-Pil Son
IPC分类号： G06F12/00 , G06F12/1009 , G06F3/06 , G11C7/10 , G11C29/42
摘要： A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.
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公开(公告)号：US10002668B2
公开(公告)日：2018-06-19
申请号：US15730379
申请日：2017-10-11
发明人： Jong-Pil Son , Uk-Song Kang
CPC分类号： G11C16/102 , G06F13/16 , G06F13/1673 , Y02D10/14
摘要： A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.
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公开(公告)号：US09727412B2
公开(公告)日：2017-08-08
申请号：US14729656
申请日：2015-06-03
发明人： Jong-Pil Son , Chul-Woo Park , Seong-Jin Jang , Hoi-Ju Chung , Sang-Uhn Cha
CPC分类号： G06F11/1008 , G06F11/1004 , G06F11/1024 , G06F11/1068 , G06F11/1666 , G11C2029/0411
摘要： A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.
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公开(公告)号：US09653141B2
公开(公告)日：2017-05-16
申请号：US14858140
申请日：2015-09-18
发明人： Sang-Yun Kim , Jong-Pil Son , Su-A Kim , Chul-Woo Park , Hong-Sun Hwang
IPC分类号： G06F12/00 , G11C11/406 , G11C11/408 , G11C11/4096
CPC分类号： G11C11/40615 , G11C11/40611 , G11C11/40618 , G11C11/40622 , G11C11/408 , G11C11/4096 , G11C2211/4061
摘要： A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.
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5.发明授权公开(公告)号：US10818375B2
公开(公告)日：2020-10-27
申请号：US16028783
申请日：2018-07-06
发明人： Jong-Pil Son , Kyo-Min Sohn
摘要： A semiconductor memory device which includes a memory cell array, an error injection register set, a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit set is associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.
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公开(公告)号：US10211123B2
公开(公告)日：2019-02-19
申请号：US15678197
申请日：2017-08-16
发明人： Jong-Pil Son
IPC分类号： H01L23/373 , H01L23/36 , H01L25/18 , H01L27/118 , H01L27/108 , H01L23/535 , H01L23/00 , H05K1/18 , H01L21/48 , H01L23/495 , H01L23/367 , H01L23/538 , H01L25/065 , H01L23/31 , H01L23/40
摘要： A semiconductor memory device includes an integrated circuit (IC) chip structure, wherein the IC chip includes a substrate, a memory cell disposed on the substrate, and a local well disposed on the substrate, wherein a conductivity type of the local well is different from a conductivity type of the substrate, a wiring stack structure disposed on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the local well through a thermal interconnector, and a heat transfer structure connected to the thermal dispersion pattern for transferring heat to the thermal dispersion pattern from a heat source.
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公开(公告)号：US20180143909A1
公开(公告)日：2018-05-24
申请号：US15633889
申请日：2017-06-27
发明人： Jae-Don Lee , Min-Kyu Jeong , Jong-Pil Son
IPC分类号： G06F12/1009
CPC分类号： G06F12/1009 , G06F3/0646 , G06F3/0647 , G06F2212/1008 , G06F2212/1024 , G06F2212/65 , G06F2212/657 , G11C7/1066 , G11C29/42 , Y02D10/13
摘要： A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.
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8.发明授权公开(公告)号：US09953702B2
公开(公告)日：2018-04-24
申请号：US15594891
申请日：2017-05-15
发明人： Jong-Pil Son
CPC分类号： G11C11/419 , G06F11/1048 , G11C7/08 , G11C7/18 , G11C29/04 , G11C29/42 , G11C2029/0411
摘要： A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The control logic circuit generates an internal processing mode signal in response to a command from a memory controller. The internal processing circuit selectively performs the internal processing operation on a first set of data read from the memory cell array to output a processing result data, in response to the internal processing mode signal. The error correction circuit performs an error correction code (ECC) encoding on the processing result data to generate a second parity data and stores the processing result data and the second parity data in the memory cell array. The error correction circuit generates the second parity data by selecting the same ECC of a plurality of ECCs as a first ECC.
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9.发明授权公开(公告)号：US09805827B2
公开(公告)日：2017-10-31
申请号：US14817212
申请日：2015-08-04
发明人： Jong-Pil Son , Chul-Woo Park , Hoi-Ju Chung , Sang-Uhn Cha , Seong-Jin Jang
IPC分类号： G11C11/16 , G11C11/4096 , G11C29/42 , G11C29/44
CPC分类号： G11C29/4401 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4096 , G11C29/42 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.
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公开(公告)号：US09805802B2
公开(公告)日：2017-10-31
申请号：US15264774
申请日：2016-09-14
发明人： Jong-Pil Son , Uk-Song Kang
CPC分类号： G11C16/102 , G06F13/16 , G06F13/1673
摘要： A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.
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