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    Memory device and memory system having the same
    3.
    发明授权
    Memory device and memory system having the same 有权

    公开(公告)号：US09685218B2

    公开(公告)日：2017-06-20

    申请号：US15236895

    申请日：2016-08-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Si-Hong Kim ,  Kwang-Il Park ,  Jae-Youn Youn

    IPC: G11C7/10 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408

    CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

    Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

    Memory device and memory system having the same
    4.
    发明授权
    Memory device and memory system having the same 有权
    存储器件和存储器系统具有相同的功能

    公开(公告)号：US09536586B2

    公开(公告)日：2017-01-03

    申请号：US14514416

    申请日：2014-10-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Si-Hong Kim ,  Kwang-Il Park ,  Jae-Youn Youn

    IPC: G11C7/10 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4076

    CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

    Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

    Abstract translation: 存储器件包括存储单元阵列，集中访问的行检测电路和刷新控制电路。 存储单元阵列包括多个存储单元行。 集中访问的行检测电路基于多个存储单元行中的每一个的累积访问时间，生成指示多个存储单元行中的集中访问的存储单元行的集中访问的行地址。 当从集中访问的行检测单元接收到集中访问的行地址时，刷新控制单元优先刷新与由强行访问的行地址指示的集中访问的存储单元行相邻的相邻存储单元行。 存储器件有效地降低了数据丢失率。

    Semiconductor memory devices and memory systems including the same
    9.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US09552867B2

    公开(公告)日：2017-01-24

    申请号：US14588496

    申请日：2015-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo Sohn ,  Uk-Song Kang ,  Kwang-Il Park ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jae-Youn Youn

    IPC: G06F3/06 ,  G11C11/408 ,  G11C5/02 ,  G11C7/02

    CPC classification number: G11C11/4087 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4085

    Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

    Abstract translation: 半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。 存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。 控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。 控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。 第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。 因此，可以补偿增加的定时参数，并且可以增加并行性。

    Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof
    10.
    发明授权
    Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof 有权
    能够缓解相邻存储单元的干扰的易失性存储器件及其刷新方法

    公开(公告)号：US09087602B2

    公开(公告)日：2015-07-21

    申请号：US14219374

    申请日：2014-03-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Youn Youn ,  Su-A Kim ,  Chul-Woo Park ,  Young-Soo Sohn

    IPC: G11C7/20 ,  G11C11/406

    CPC classification number: G11C11/40615 ,  G11C7/02 ,  G11C7/1063 ,  G11C11/40611 ,  G11C11/40618

    Abstract: Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.

    Abstract translation: 提供了一种易失性存储器件的刷新方法。 该方法包括：随着对第一存储器区域的访问次数的增加，检测影响第二存储器区域的多个干扰; 当检测到的干扰次数达到参考值时，将来自易失性存储器件的警报信号输出到易失性存储器件的外部; 以及响应于所述警报信号对所述第二存储区域执行刷新操作。

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