INTERFACE CIRCUIT AND PACKET TRANSMISSION METHOD THEREOF
    1.
    发明申请
    INTERFACE CIRCUIT AND PACKET TRANSMISSION METHOD THEREOF 审中-公开
    接口电路和分组传输方法

    公开(公告)号:US20160041936A1

    公开(公告)日:2016-02-11

    申请号:US14697815

    申请日:2015-04-28

    CPC classification number: G06F13/4027 G06F12/0866 G06F13/4282 G06F2212/222

    Abstract: A packet transmission method includes packaging a plurality of data in the form of a payload; storing information on whether the plurality of data are packaged in a header, the payload or a CRC area including a transmission error check code of the plurality of data; combining the header, the payload, and the CRC area with each other to generate a transaction layer packet; and outputting a packet including the transaction layer packet.

    Abstract translation: 分组传输方法包括以有效载荷的形式封装多个数据; 存储关于所述多个数据是否被封装在报头中的信息,所述有效载荷或包括所述多个数据的传输错误校验码的CRC区域; 将报头,有效载荷和CRC区域相互组合以生成事务层分组; 并输出包括事务层分组的分组。

    EMBEDDED MEMORY DEVICE AND MEMORY CONTROLLER INCLUDING THE SAME
    2.
    发明申请
    EMBEDDED MEMORY DEVICE AND MEMORY CONTROLLER INCLUDING THE SAME 有权
    嵌入式存储器件和存储器控制器,包括它们

    公开(公告)号:US20140369137A1

    公开(公告)日:2014-12-18

    申请号:US14231856

    申请日:2014-04-01

    Abstract: An embedded memory device includes a mask ROM including a plurality of mask ROM cells and an address decoder configured to decode an address of the plurality of mask ROM cells; and an e-fuse memory configured to replace a part of data stored in the mask ROM with replacement data, the e-fuse memory including, a plurality of e-fuse memory cells configured to store the replacement data, and an e-fuse address selector configured to decode an address of the plurality of e-fuse memory cells and to selectively cause data of one or more of the plurality of e-fuse memory cells to be output based on the decoding result.

    Abstract translation: 一种嵌入式存储器件包括:掩模ROM,包括多个掩模ROM单元;以及地址解码器,被配置为对多个掩模ROM单元的地址进行解码; 以及电子熔丝存储器,其被配置为用替换数据替换存储在掩模ROM中的一部分数据,所述电子熔丝存储器包括被配置为存储替换数据的多个电子熔丝存储器单元和电子熔丝地址 所述选择器被配置为解码所述多个电子熔丝存储单元的地址,并且基于所述解码结果选择性地引起所述多个电子熔丝存储器单元中的一个或多个的数据的输出。

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