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公开(公告)号:US20140131895A1
公开(公告)日:2014-05-15
申请号:US13826612
申请日:2013-03-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Won-Hyung SONG , Kyoungsun KIM , Yong-jin KIM , Jaejun LEE , Sangseok KANG , Jungjoon LEE
IPC: H01L25/07
CPC classification number: G11C5/04 , G06F13/102 , G06F13/4068 , G06F13/42 , G11C5/02 , H01L24/73 , H01L25/0657 , H01L25/074 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/12044 , H01L2924/15311 , H01L2924/1533 , H01L2924/15331 , H01L2924/00012 , H01L2924/00
Abstract: A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.
Abstract translation: 提供了一种包括印刷电路板的存储器模块; 设置在印刷电路板的一个表面上的第一半导体封装; 以及设置在所述印刷电路板的另一个表面上的第二半导体封装,所述第一半导体封装和所述第二半导体封装具有形成等级的半导体管芯。 由第一半导体封装形成的多个等级由与第二半导体封装形成的等级数不同。 形成相同行列的半导体封装共同接收芯片选择信号,形成其他级别的半导体封装接收不同的芯片选择信号。
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公开(公告)号:US20160275995A1
公开(公告)日:2016-09-22
申请号:US15168961
申请日:2016-05-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Won-Hyung SONG , Kyoungsun KIM , Yong-Jin KIM , Jaejun LEE , Sangseok KANG , Jungjoon LEE
CPC classification number: G11C5/04 , G06F13/102 , G06F13/4068 , G06F13/42 , G11C5/02 , H01L24/73 , H01L25/0657 , H01L25/074 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/12044 , H01L2924/15311 , H01L2924/1533 , H01L2924/15331 , H01L2924/00012 , H01L2924/00
Abstract: A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.
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