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公开(公告)号:US20240249775A1
公开(公告)日:2024-07-25
申请号:US18591728
申请日:2024-02-29
发明人: Jaeho Ahn , Jiwon Kim , Sungmin Hwang , Joonsung Lim , Sukkang Sung
IPC分类号: G11C16/10 , G11C16/26 , H01L23/48 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
CPC分类号: G11C16/10 , G11C16/26 , H01L23/481 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
摘要: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.
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公开(公告)号:US11895840B2
公开(公告)日:2024-02-06
申请号:US17895182
申请日:2022-08-25
发明人: Woosung Yang , Byungjin Lee , Bumkyu Kang , Joonsung Lim
IPC分类号: H10B43/27 , H01L23/00 , G11C7/18 , H01L23/522 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
CPC分类号: H10B43/27 , G11C7/18 , H01L23/5226 , H01L24/09 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
摘要: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.
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公开(公告)号:US20230080606A1
公开(公告)日:2023-03-16
申请号:US17852812
申请日:2022-06-29
发明人: Seungmin Lee , Junhyoung Kim , Kangmin Kim , Joonsung Lim
IPC分类号: H01L27/11573 , H01L27/11519 , H01L23/528 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要: A semiconductor device may include: a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a plate pattern on the peripheral circuit structure and having a gap; and a stack structure on the plate pattern and including a first stack region and a second stack region. The first stack region may include gate electrodes stacked in a vertical direction perpendicular to an upper surface of the semiconductor substrate, and the second stack region may include both a conductor stack region including conductive layers stacked in the vertical direction and an insulator stack region including molded insulating layers at substantially the same height level as the conductive layers. The semiconductor device may also include vertical memory structure that extends through the first stack region; and source contact plugs electrically connected to at least one of the conductive layers of the conductor stack region and contacting the plate pattern.
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公开(公告)号:US20220139821A1
公开(公告)日:2022-05-05
申请号:US17376240
申请日:2021-07-15
发明人: Sungmin HWANG , Jiwon Kim , Jaeho Ahn , Joonsung Lim , Sukkang Sung
IPC分类号: H01L23/522 , H01L25/065 , H01L25/18 , H01L23/00
摘要: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.
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公开(公告)号:US12033706B2
公开(公告)日:2024-07-09
申请号:US17873739
申请日:2022-07-26
发明人: Junyeong Seok , Younggul Song , Eunchu Oh , Byungchul Jang , Joonsung Lim
CPC分类号: G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/16
摘要: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.
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公开(公告)号:US20230005949A1
公开(公告)日:2023-01-05
申请号:US17720453
申请日:2022-04-14
发明人: Seungmin Lee , Kangmin Kim , Junhyoung Kim , Yonghoon Son , Joonsung Lim
IPC分类号: H01L27/11575 , H01L23/535 , H01L49/02 , H01L27/11582 , H01L27/11573
摘要: A semiconductor device includes a first structure including a peripheral circuit and a second structure on the first structure. The second structure includes: a stack structure including first and second stack structures; separation structures passing through the first stack structure; a memory vertical structure between the separation structures and passing through the first stack structure; and a capacitor including first and second capacitor electrodes passing through the second stack structure and extending parallel to each other. The first stack structure includes spaced apart gate electrodes and interlayer insulating layers alternately stacked therewith. The second stack structure includes spaced apart first insulating layers, and second insulating layers alternately stacked therewith. Each of the first and second capacitor electrodes has a linear shape. The first and second insulating layers include a different material from each other. The second insulating layers include the same material as the interlayer insulating layers.
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公开(公告)号:US11251196B2
公开(公告)日:2022-02-15
申请号:US16749255
申请日:2020-01-22
发明人: Jaeho Ahn , Woosung Yang , Joonsung Lim , Sungmin Hwang
IPC分类号: H01L27/11582 , H01L27/11556 , H01L23/528 , H01L27/11526 , H01L23/522 , H01L25/065 , H01L23/00 , H01L27/11573
摘要: An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.
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公开(公告)号:US11715684B2
公开(公告)日:2023-08-01
申请号:US17376240
申请日:2021-07-15
发明人: Sungmin Hwang , Jiwon Kim , Jaeho Ahn , Joonsung Lim , Sukkang Sung
IPC分类号: H01L27/115 , H01L23/31 , H01L23/522 , H01L23/00 , H01L25/065 , H01L25/18 , H10B43/27
CPC分类号: H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/5228 , H01L24/20 , H01L24/24 , H01L25/0657 , H01L25/18 , H01L2224/2105 , H01L2224/24146 , H01L2924/1431 , H01L2924/14511 , H10B43/27
摘要: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.
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公开(公告)号:US20230052161A1
公开(公告)日:2023-02-16
申请号:US17873739
申请日:2022-07-26
发明人: Junyeong Seok , Younggul Song , Eunchu Oh , Byungchul Jang , Joonsung Lim
摘要: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.
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公开(公告)号:US11581333B2
公开(公告)日:2023-02-14
申请号:US17573015
申请日:2022-01-11
发明人: Jaeho Ahn , Woosung Yang , Joonsung Lim , Sungmin Hwang
IPC分类号: H01L27/11582 , H01L27/11556 , H01L23/528 , H01L27/11526 , H01L23/522 , H01L25/065 , H01L23/00 , H01L27/11573
摘要: An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.
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