公开(公告)号：US10672792B2

公开(公告)日：2020-06-02

申请号：US16266409

申请日：2019-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangyoon Choi ,  Gilsung Lee ,  Dong-Sik Lee ,  Yongsik Yim ,  Eunsuk Cho

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28

Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.

公开(公告)号：US10903236B2

公开(公告)日：2021-01-26

申请号：US16663228

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangyoon Choi ,  Dong-Sik Lee ,  Jongwon Kim ,  Gilsung Lee ,  Eunsuk Cho ,  Byungyong Choi ,  Sung-Min Hwang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/04 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/02

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.

公开(公告)号：US20190371808A1

公开(公告)日：2019-12-05

申请号：US16266409

申请日：2019-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangyoon Choi ,  Gilsung Lee ,  Dong-Sik Lee ,  Yongsik Yim ,  Eunsuk Cho

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28

Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.