公开(公告)号：US20130200487A1

公开(公告)日：2013-08-08

申请号：US13834847

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Moon PARK ,  Jae Hwang SIM ,  Keon Soo KIM

IPC: H01L29/06

CPC classification number: H01L29/0657 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529

Abstract: A pattern structure for a semiconductor device includes a plurality of first patterns, each of the first patterns extending in a first direction in the shape of a line, neighboring first patterns being spaced apart from each other by a gap distance, the plurality of first patterns including a plurality of trenches in parallel with the line shapes, respective trenches being between neighboring first patterns, the plurality of trenches including long trenches and short trenches alternately arranged in a second direction substantially perpendicular to the first direction, and at least a second pattern, the second pattern being coplanar with the first pattern, end portions of the first patterns being connected to the second pattern.

Abstract translation: 用于半导体器件的图案结构包括多个第一图案，每个第一图案沿着第一方向延伸为线状，相邻的第一图案彼此间隔开间隔距离，多个第一图案 包括与所述线形平行的多个沟槽，相应的沟槽位于相邻的第一图案之间，所述多个沟槽包括沿基本上垂直于所述第一方向的第二方向交替布置的长沟槽和短沟槽，以及至少第二图案， 所述第二图案与所述第一图案共面，所述第一图案的端部连接到所述第二图案。

公开(公告)号：US20170309486A1

公开(公告)日：2017-10-26

申请号：US15644931

申请日：2017-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Seok JUNG ,  Joon Hee LEE ,  Keon Soo KIM ,  Sun Yeong LEE

IPC: H01L21/28 ,  H01L29/66 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/78 ,  H01L27/11582

CPC classification number: H01L21/28008 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.