公开(公告)号：US20140287564A1

公开(公告)日：2014-09-25

申请号：US14287546

申请日：2014-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum-Seok Park ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Hong-Bum Park

IPC: H01L29/66 ,  H01L29/08

CPC classification number: H01L29/66621 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.

Abstract translation: 提供了半导体器件，其包括具有从第一表面的相对侧凹入的第一表面和第二表面的衬底，形成在第一表面上并具有栅极绝缘层和栅电极的栅极图案，碳掺杂硅缓冲层 形成在第二表面上，以及掺杂有n型掺杂剂或p型掺杂剂的源极和漏极区，其外延生长在硅缓冲层上以从栅极绝缘层的顶表面升高。

公开(公告)号：US09112015B2

公开(公告)日：2015-08-18

申请号：US13921616

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum-Seok Park ,  Jung-Ho Yoo ,  Woo-Bin Song ,  Byeong-Chan Lee

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/823814 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: In a semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate structure crossing an active region of a silicon substrate. Spacers are provided on both sides of the gate structure, respectively. Silicon patterns fill up recessed portions of the silicon substrate and on both sides of the spacers and has a shape protruding higher than a bottom surface of the gate structure, a lower edge of the protruded portion partially makes contact with a top surface of the isolation region, a first side and a second side of each of the silicon patterns, which are opposite to each other in a channel width direction in the gate structure, are inclined toward an inside of the active region. A highly doped impurity region is provided in the silicon patterns and doped with an N type impurity. The semiconductor device represents superior threshold voltage characteristics.

Abstract translation: 在半导体器件及其制造方法中，半导体器件包括与硅衬底的有源区交叉的栅极结构。 分别设置在门结构的两侧。 硅图案填充硅衬底的凹陷部分并且在间隔物的两侧上并且具有高于栅极结构的底表面突出的形状，突出部分的下边缘部分地与隔离区域的顶表面接触 ，在栅极结构中的沟道宽度方向上彼此相对的每个硅图案的第一侧和第二侧朝向有源区域的内部倾斜。 在硅图案中提供高掺杂杂质区，并掺杂有N型杂质。 半导体器件表现出优异的阈值电压特性。