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1.发明申请公开(公告)号：US20180331100A1
公开(公告)日：2018-11-15
申请号：US16028272
申请日：2018-07-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hye-Lan Lee , Sang-Bom Kang , Jae-Jung Kim , Moon-Kyu Park , Jae-Yeol Song , June-Hee Lee , Yong-Ho Ha , Sang-Jin Hyun
IPC: H01L27/088 , H01L21/84 , H01L29/66 , H01L29/49 , H01L21/8238 , H01L27/12 , H01L27/092 , H01L29/51 , H01L29/165
CPC classification number: H01L27/0886 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66545
Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
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公开(公告)号：US11127739B2
公开(公告)日：2021-09-21
申请号：US16028272
申请日：2018-07-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hye-Lan Lee , Sang-Bom Kang , Jae-Jung Kim , Moon-Kyu Park , Jae-Yeol Song , June-Hee Lee , Yong-Ho Ha , Sang-Jin Hyun
IPC: H01L21/8238 , H01L27/088 , H01L29/49 , H01L29/66 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/51
Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
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公开(公告)号：US20140287564A1
公开(公告)日：2014-09-25
申请号：US14287546
申请日：2014-05-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keum-Seok Park , Seung-Hun Lee , Byeong-Chan Lee , Sang-Bom Kang , Hong-Bum Park
CPC classification number: H01L29/66621 , H01L29/0847 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
Abstract: Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.
Abstract translation: 提供了半导体器件，其包括具有从第一表面的相对侧凹入的第一表面和第二表面的衬底，形成在第一表面上并具有栅极绝缘层和栅电极的栅极图案，碳掺杂硅缓冲层 形成在第二表面上，以及掺杂有n型掺杂剂或p型掺杂剂的源极和漏极区，其外延生长在硅缓冲层上以从栅极绝缘层的顶表面升高。
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Patent Agency Ranking
公开(公告)号：US20150145056A1
公开(公告)日：2015-05-28
申请号：US14565903
申请日：2014-12-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung-Chan Lee , Seung-Jae Lee , Sang-Bom Kang , Dae-Young Kwak , Myeong-Cheol Kim , Yong-Ho Jeon
IPC: H01L27/088
CPC classification number: H01L27/088 , H01L21/764 , H01L27/0886 , H01L27/1116 , H01L27/1211
Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.
Abstract translation: 一种半导体器件，包括：设置在衬底的周边区域中的第一栅极图案; 设置在所述基板的单元区域中的第二栅极图案; 形成在第一栅极图案的侧壁上的第一绝缘体; 以及形成在所述第二栅极图案的侧壁上的第二绝缘体，其中所述第一绝缘体的介电常数不同于所述第二绝缘体的介电常数，并且其中所述第二绝缘体的高度大于所述第二栅极图案的高度 。
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公开(公告)号：US20140203335A1
公开(公告)日：2014-07-24
申请号：US14155579
申请日：2014-01-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Yeol Song , June-Hee Lee , Hye-Lan Lee , Sang-Jin Hyun , Sang-Bom Kang
CPC classification number: H01L29/78 , H01L21/28088 , H01L21/823842 , H01L27/1104 , H01L29/51 , H01L29/6681
Abstract: A semiconductor device includes an insulating film on a substrate and including a trench, a gate insulating film in the trench, a DIT (Density of Interface Trap) improvement film on the gate insulating film to improve a DIT of the substrate, and a first conductivity type work function adjustment film on the DIT improvement film. Related methods of forming semiconductor devices are also disclosed.
Abstract translation: 半导体器件包括在衬底上的绝缘膜，其包括沟槽，沟槽中的栅极绝缘膜，栅极绝缘膜上的DIT（界面陷阱密度）改进膜，以改善衬底的DIT，以及第一导电性 DIT改进膜上的工作功能调整膜。 还公开了形成半导体器件的相关方法。
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公开(公告)号：US09305921B2
公开(公告)日：2016-04-05
申请号：US14565903
申请日：2014-12-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung-Chan Lee , Seung-Jae Lee , Sang-Bom Kang , Dae-Young Kwak , Myeong-Cheol Kim , Yong-Ho Jeon
IPC: H01L31/058 , H01L27/088 , H01L21/764 , H01L27/11 , H01L27/12
CPC classification number: H01L27/088 , H01L21/764 , H01L27/0886 , H01L27/1116 , H01L27/1211
Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.
Abstract translation: 一种半导体器件，包括：设置在衬底的周边区域中的第一栅极图案; 设置在所述基板的单元区域中的第二栅极图案; 形成在第一栅极图案的侧壁上的第一绝缘体; 以及形成在所述第二栅极图案的侧壁上的第二绝缘体，其中所述第一绝缘体的介电常数不同于所述第二绝缘体的介电常数，并且其中所述第二绝缘体的高度大于所述第二栅极图案的高度 。
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公开(公告)号：US09299811B2
公开(公告)日：2016-03-29
申请号：US14519771
申请日：2014-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wook-Je Kim , Jae-Yup Chung , Jong-Seo Hong , Cheol Kim , Hee-Soo Kang , Hyun-Jo Kim , Hee-Don Jeong , Soo-Hun Hong , Sang-Bom Kang , Myeong-Cheol Kim , Young-Su Chung
IPC: H01L29/66 , H01L21/8234 , H01L29/78 , H01L29/165
CPC classification number: H01L29/66795 , H01L21/823431 , H01L21/823481 , H01L29/165 , H01L29/66545 , H01L29/7848
Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.
Abstract translation: 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。
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公开(公告)号：US20150147860A1
公开(公告)日：2015-05-28
申请号：US14519771
申请日：2014-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wook-Je Kim , Jae-Yup Chung , Jong-Seo Hong , Cheol Kim , Hee-Soo Kang , Hyun-Jo Kim , Hee-Don Jeong , Soo-Hun Hong , Sang-Bom Kang , Myeong-Cheol Kim , Young-Su Chung
IPC: H01L29/66
CPC classification number: H01L29/66795 , H01L21/823431 , H01L21/823481 , H01L29/165 , H01L29/66545 , H01L29/7848
Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.
Abstract translation: 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。
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